IDT82V2108PX IDT, Integrated Device Technology Inc, IDT82V2108PX Datasheet - Page 124

• Manufacturer Part Number: IDT82V2108PX
• Description: IC FRAMER T1/J1/E1 8CH 128-PQFP
• Manufacturer: IDT, Integrated Device Technology Inc

Specifications of IDT82V2108PX

• Controller Type: T1/E1/J1 Framer
• Interface: Parallel
• Voltage - Supply: 2.97 V ~ 3.63 V
• Current - Supply: 160mA
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 128-MQFP, 128-PQFP
• Screening Level: Industrial
• Mounting: Surface Mount
• Operating Temperature (min): -40C
• Operating Temperature (max): 85C
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Other names: 82V2108PX

IDT82V2108
4.2.4
reference.
4.2.4.1
mat. Before using the HDLC#2 Receive, the TXCISEL (b3, T1/J1-00DH)
must be set to ‘0’ to enable the HDLC data link position for receive path.
one of the two HDLC Receive data links must be chosen in the
RHDLCSEL[1:0] (b7~6, T1/J1-00DH). The RHDLC #1 can only extract
from F-bit of each odd frame. The RHDLC #2 can be set to extract from
even and/or odd frames, from any channel, and from any bit. The follow
is an example for selecting the HDLC Receive data link positions in
RHDLC #2:
ers in HDLC Receive #2:
HDLC Receive should be enabled by setting the EN (b0, T1/J1-054H) to
logic 1. If needed, set the MEN (b3, T1/J1-054H) and the MM (b2, T1/J1-
054H) to determine which Address Matching Mode is used (refer to
Chapter 5.2 Register Description for details). After setting these 3 bits,
the RHDLC Primary Address Match register and the RHDLC Secondary
Address Match register should be set to proper values. If the INTC[6:0]
(b6~0, T1/J1-055H) are set, whenever the number of bytes in the
RHDLC FIFO exceeds the value set in the INTC[6:0] (b6~0, T1/J1-
055H), the INTR (b0, T1/J1-056H) will be set to logic 1. This interrupt will
persist until the RHDLC FIFO becomes empty. Setting the INTE (b7, T1/
J1-055H) to logic 1 allows the internal interrupt status to be propagated
to the INT output pin.
received in a polled or interrupt driven mode.
- Interrupt Driven Mode
asserted, the source of the interrupt should be identified firstly by read-
ing the Interrupt ID register and Interrupt Source registers. If the source
of the interrupt is HDLC Receive, the Interrupt Service procedure will be
carried out as shown in Figure 79.
- Polling Mode
Figure 79, except that the entry of the service is from a local timer rather
than an interrupt.
Operation
In this chapter, some common operation examples are given for
In T1/J1 mode, the HDLC Receive can only be used in the ESF for-
Since two HDLC Receive data links are integrated in one framer,
a. Extract the HDLC data link from all bits of channel 20 of all fram-
- set the TXCISEL (b3, T1/J1-00DH) to ‘0’;
- set the RHDLCSEL[1:0] (b7~6, T1/J1-00DH) to ‘01’;
- set the DL2_EVEN (b7, T1/J1-070H) to ‘1’;
- set the DL2_ODD (b6, T1/J1-070H) to ‘1’;
- set the DL2_TS[4:0] (b4~0, T1/J1-070H) to ‘10100’;
- set the DL2_BIT[7:0] (b7~0, T1/J1-071H) to ‘11111111’.
After setting the HDLC data link position properly, the selected
After setting these registers properly, the HDLC data can be
When the INTE (b7, T1/J1-055H) is set to logic 1, if the INT pin is
In the polling mode, the operation procedure is the same as
OPERATION EXAMPLE
Using HDLC Receiver
114
T1 / E1 / J1 OCTAL FRAMER
March 5, 2009