IDT82V2108PX IDT, Integrated Device Technology Inc, IDT82V2108PX Datasheet - Page 155

• Manufacturer Part Number: IDT82V2108PX
• Description: IC FRAMER T1/J1/E1 8CH 128-PQFP
• Manufacturer: IDT, Integrated Device Technology Inc

Specifications of IDT82V2108PX

• Controller Type: T1/E1/J1 Framer
• Interface: Parallel
• Voltage - Supply: 2.97 V ~ 3.63 V
• Current - Supply: 160mA
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 128-MQFP, 128-PQFP
• Screening Level: Industrial
• Mounting: Surface Mount
• Operating Temperature (min): -40C
• Operating Temperature (max): 85C
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Other names: 82V2108PX

IDT82V2108
E1 Receive Backplane Parity / F-bit Configuration (012H, 092H, 112H, 192H, 212H, 292H, 312H, 392H)
RPTYP:
the previous Basic frame is odd.
the previous Basic frame is even.
RPTYE:
FIXF:
F-bit) mode and valid when RPTYE = 0.
FIXPOL:
PTY_EXTD:
this bit.
TRI[1:0]:
Programming Information
Bit Name
Default
Bit No.
Type
This bit chooses the parity type for the receive side system data.
= 0: Even parity is employed, which means a logic one should be inserted in the first bit of TS0 of each Basic frame when the number of ‘One’s in
= 1: Odd parity is employed, which means a logic one should be inserted in the first bit of TS0 of each Basic frame when the number of ‘One’s in
This bit enables the parity for the receive side system data. The bit is invalid in Receive Clock Master Fractional E1 (with F-bit) mode.
= 0: Disable the parity on the RSDn/MRSD pin.
= 1: Enable the parity on the RSDn/MRSD pin.
This bit controls whether the parity bit position is fixed at the level defined by the FIXPOL. It is invalid in Receive Clock Master Fractional E1 (with
= 0: No action.
= 1: The setting in the FIXPOL is valid. The first bit of TS0 of each Basic frame output on the RSDn/MRSD pin is fixed with the value of FIXPOL.
This bit is invalid in Receive Clock Master Fractional E1 (with F-bit) mode and valid when the RPTYE = 0 and the FIXF = 1.
= 0: Force the first bit of TS0 of each Basic frame output on the RSDn/MRSD pin to be logic 0.
= 1: Force the first bit of TS0 of each Basic frame output on the RSDn/MRSD pin to be logic 1.
When the parity is calculated over the previous Basic frame, the first bit of TS0 on the RSDn pin can be included or not. The decision is made by
= 0: The first bit of TS0 on the RSDn/MRSD pin is not calculated.
= 1: The first bit of TS0 on the RSDn/MRSD pin is calculated.
In the Receive Multiplexed Mode, these bits of the framers that are output to the same multiplexed bus must be set to the same value.
RPTYP
R/W
7
0
RPTYE
R/W
TRI[1:0]
6
0
0 0
1 0
0 1
1 1
FIXF
R/W
5
0
Output Status on the RSDn/MRSD and RSSIGn/MRSSIG pins
FIXPOL
R/W
4
0
145
in high impedance
normal output
Reserved
Reserved
PTY_EXTD
R/W
3
0
Reserved
2
T1 / E1 / J1 OCTAL FRAMER
TRI[1]
R/W
1
0
March 5, 2009
TRI[0]
R/W
0
0