IDT82V2108PX IDT, Integrated Device Technology Inc, IDT82V2108PX Datasheet - Page 39

• Manufacturer Part Number: IDT82V2108PX
• Description: IC FRAMER T1/J1/E1 8CH 128-PQFP
• Manufacturer: IDT, Integrated Device Technology Inc

Specifications of IDT82V2108PX

• Controller Type: T1/E1/J1 Framer
• Interface: Parallel
• Voltage - Supply: 2.97 V ~ 3.63 V
• Current - Supply: 160mA
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 128-MQFP, 128-PQFP
• Screening Level: Industrial
• Mounting: Surface Mount
• Operating Temperature (min): -40C
• Operating Temperature (max): 85C
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Other names: 82V2108PX

IDT82V2108
3.10.2
J1-050H) must be set to activate the setting in the indirect registers
(from 01H to 48H). The following methods can be used for test on a per-
channel basis:
data of one of the eight framers will be extracted to the PRBS Generator/
Detector when the RXPATGEN (b2, T1/J1-00FH) is ‘0’. The received
data can be extracted in framed or unframed mode, as determined by
the UNF_DET (b0, T1/J1-00FH). In unframed mode, all the 24 channels
and the F-bit are extracted and the per-channel configuration in the
TEST (b3, T1/J1-RPLC-indirect registers - 01~18H) is ignored. In
framed mode, the received data will only be extracted on the channel
specified by the TEST (b3, T1/J1-RPLC-indirect registers - 01~18H).
Fractional T1/J1 signal can also be extracted in the specified channel
when the Nx56k_DET (b3, T1/J1-00FH) is set. Refer to Chapter 3.12
PRBS Generator / Detector (PRGD) for details.
the value in the DTRK[7:0] (b7~0, T1/J1-RPLC-indirect registers -
19~30H) when the DTRKC (b6, T1/J1-RPLC-indirect registers -
01~18H) of the corresponding channel is logic 1. (When it is out of SF/
ESF synchronization, the value in the DTRK[7:0] (b7~0, T1/J1-RPLC-
indirect registers - 19~30H) will replace the data automatically if the
AUTOOOF (b1, T1/J1-000H) is set. Or, when the RED alarm is
declared, the value in the DTRK[7:0] (b7~0, T1/J1-RPLC-indirect regis-
ters - 19~30H) will replace the data automatically if the AUTORED (b2,
T1/J1-000H) is set. These two kinds of data replacements can be exe-
cuted even if the PCCE (b0, T1/J1-050H) is disabled and they replace
all the channels.)
the milliwatt pattern when the DMW (b5, T1/J1-RPLC-indirect register -
01~18H) of the corresponding channel allows. (The milliwatt is µ-law.
Refer to Table 9.)
tern from the PRBS Generator/Detector will replace the received data of
one of the eight framers when the RXPATGEN (b2, T1/J1-00FH) is ‘1’.
The test pattern can replace the received data in framed or unframed
mode, as determined by the UNF_GEN (b1, T1/J1-00FH). In unframed
mode, all the 24 channels and the F-bit are replaced and the per-chan-
nel configuration in the TEST (b3, T1/J1-RPLC-indirect registers -
01~18H) is ignored. In framed mode, the received data will only be
replaced on the channel specified by the TEST (b3, T1/J1-RPLC-indirect
registers - 01~18H). Fractional T1/J1 signal can also be replaced in the
specified channel when the Nx56k_GEN (b4, T1/J1-00FH) is set. Refer
to Chapter 3.12 PRBS Generator / Detector (PRGD) for details.
that will be output on the RSDn/MRSD pin when the SIGNINV and the
INVERT (b4 & b7, T1/J1-RPLC-indirect registers - 01~18H) of the corre-
sponding channel are set.
indirect registers - 01~18H) when the FIX (b1, T1/J1-RPLC-indirect reg-
isters - 01~18H) of the corresponding channel is logic 1.
ity.)
Functional Description
To enable the test for the received data stream, the PCCE (b0, T1/
- Selected by the PRGDSEL[2:0] (b7~5, T1/J1-00FH), the received
- Replace the data that will be output on the RSDn/MRSD pin with
- Replace the data that will be output on the RSDn/MRSD pin with
- Selected by the PRGDSEL[2:0] (b7~5, T1/J1-00FH), the test pat-
- Invert the most significant bit and/or the other bits in a channel
- Fix the signaling bit with the value in the POL (b0, T1/J1-RPLC-
(The above methods are arranged from highest to lowest in prior-
T1/J1 MODE
29
pin with the value in the A, B, C, D (b3~0, T1/J1-RPLC-indirect registers
- 31~48H) when the STRKC (b7, T1/J1-RPLC-indirect registers -
31~48H) of the corresponding channel is logic 1.
ting in the DTRK[7:0] (b7~0, T1/J1-RPLC-indirect registers - 19~30H)
and the A, B, C, D (b3~0, T1/J1-RPLC-indirect registers - 31~48H)
respectively when the IMTKC (b0, T1/J1-001H) is set. To enable this
function, the PCCE (b0, T1/J1-050H) must be set to ‘1’.
written into the indirect registers is in the D[7:0] (b7~0, T1/J1-053H). The
read or write operation is determined by the R/WB (b7, T1/J1-052H).
Before the read/write operation is completed, the BUSY (b7, T1/J1-
051H) will be set. New operations on the indirect registers can only be
implemented when the BUSY (b7, T1/J1-051H) is cleared. The read/
write cycle is 650 ns.
- Replace the signaling that will be output on the RSSIGn/MRSSIG
The data and signaling of all channels will be replaced with the set-
Addressed by the A[6:0] (b6~0, T1/J1-052H), the data read from or
T1 / E1 / J1 OCTAL FRAMER
March 5, 2009