ADUC7033BCPZ-8L Analog Devices Inc, ADUC7033BCPZ-8L Datasheet - Page 114

• Manufacturer Part Number: ADUC7033BCPZ-8L
• Description: IC MCU FLASH 96K ANLG I/O 48LFCS
• Manufacturer: Analog Devices Inc
• Type: Battery Managementr

Specifications of ADUC7033BCPZ-8L

• Input Type: Logic
• Output Type: Logic
• Interface: UART, SPI
• Current - Supply: 20mA
• Mounting Type: Surface Mount
• Package / Case: 48-LFCSP
• For Use With: EVAL-ADUC7033QSPZ - EVAL DEV QUICK START ADUC7033
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

ADuC7033
SERIAL PERIPHERAL INTERFACE
The ADuC7033 features a complete hardware serial peripheral
interface (SPI) on-chip. SPI is an industry standard synchronous
serial interface that allows eight bits of data to be synchronously
transmitted and received simultaneously, that is, full duplex.
The SPI interface is only operational with core clock divider bits
(POWCON[2:0] = 0 or 1).
The SPI port can be configured for master or slave operation
and consists of four pins that are multiplexed with four GPIOs.
The four SPI pins are MISO, MOSI, SCLK, and SS . The pins to
which these signals are connected are shown in
Table 87. SPI Output Pins
Pin
GPIO_0 (GPIO Mode 1)
GPIO_1 (GPIO Mode 1)
GPIO_2 (GPIO Mode 1)
GPIO_3 (GPIO Mode 1)
MISO (MASTER IN, SLAVE OUT DATA I/O PIN)
The master in, slave out (MISO) pin is configured as an input
line in master mode and an output line in slave mode. The
MISO line on the master (data in) should be connected to the
MISO line in the slave device (data out). The data is transferred
as byte-wide (8-bit) serial data, MSB first.
MOSI (MASTER OUT, SLAVE IN PIN)
The MOSI (master out, slave in) pin is configured as an output
line in master mode and an input line in slave mode. The MOSI
line on the master (data out) should be connected to the MOSI
line in the slave device (data in). The data is transferred as byte-
wide (8-bit) serial data, MSB first.
SCLK (SERIAL CLOCK I/O PIN)
The master serial clock (SCLK) is used to synchronize the data
being transmitted and received through the MOSI SCLK
period. Therefore, a byte is transmitted/received after eight
SCLK periods. The SCLK pin is configured as an output in
master mode and as an input in slave mode.
Signal
SS
SCLK
MISO
MOSI
Description
Chip select
Serial clock
Master out, slave in
Master in, slave out
Table 87
.
Rev. B | Page 114 of 140
In master mode, polarity and phase of the clock is controlled by
the SPICON register, and the bit rate is defined in the SPIDIV
register using the SPI baud rate calculation, as follows:
The maximum speed of the SPI clock is dependent on the clock
divider bits and is summarized in Table 88.
Table 88. SPI Speed vs. Clock Divider Bits in Master Mode
CD Bits
SPIDIV
Maximum SCLK
In slave mode, the SPICON register must be configured with
the phase and polarity of the expected input clock. The slave
accepts data from an external master up to 5.12 Mb at CD = 0.
The formula to determine the maximum speed is as follows:
In both master and slave modes, data is transmitted on one edge
of the SCL signal and sampled on the other. Therefore, it is
important that the polarity and phase are configured the same
for the master and slave devices.
CHIP SELECT (SS) INPUT PIN
In SPI slave mode, a transfer is initiated by the assertion of SS ,
an active low input signal. The SPI port then transmits and
receives eight bits of data until the transfer is concluded by the
deassertion of SS . In slave mode, SS is always an input.
SPI REGISTER DEFINITIONS
The following MMR registers are used to control the SPI
interface:
SPICON: 16-bit control register
SPISTA: 8-bit read-only status register
SPIDIV: 8-bit serial clock divider register
SPITX: 8-bit write-only transmit register
SPIRX: 8-bit read-only receive register
f
f
SERIAL
SERIAL
CLOCK
CLOCK
=
=
2
×
20
f
1 (
HCLK
.
4
48
+
SPIDIV
MHz
)
0
0x05
1.667 MHz
1
0x0B
0.833 MHz
(3)