ADUC7033BCPZ-8L Analog Devices Inc, ADUC7033BCPZ-8L Datasheet - Page 56

• Manufacturer Part Number: ADUC7033BCPZ-8L
• Description: IC MCU FLASH 96K ANLG I/O 48LFCS
• Manufacturer: Analog Devices Inc
• Type: Battery Managementr

Specifications of ADUC7033BCPZ-8L

• Input Type: Logic
• Output Type: Logic
• Interface: UART, SPI
• Current - Supply: 20mA
• Mounting Type: Surface Mount
• Package / Case: 48-LFCSP
• For Use With: EVAL-ADUC7033QSPZ - EVAL DEV QUICK START ADUC7033
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

ADuC7033
Current Channel ADC Data Register
Name:
Address:
Default
Value:
Access:
Function:
Voltage Channel ADC Data Register
Name:
Address:
Default
Value:
Access:
Function:
Temperature Channel ADC Data Register
Name:
Address:
Default
Value:
Access:
Function:
ADC0DAT
0x0000
Read only
This ADC Data MMR holds the 16-bit conversion
result from the I-ADC. The ADC does not update
this MMR if the ADC0 conversion result ready bit
(ADCSTA[0]) is set. A read of this MMR by the
MCU clears all asserted ready flags
(ADCSTA[2:0]).
ADC1DAT
0x0000
Read only
This ADC Data MMR holds the 16-bit voltage
conversion result from the V/T-ADC. The ADC
does not update this MMR if the voltage conversion
result ready bit (ADCSTA[1]) is set. If I-ADC is not
active, a read of this MMR by the MCU clears all
asserted ready flags (ADCSTA[2:1]).
ADC2DAT
0x0000
Read only
conversion result from the V/T-ADC. The ADC
does not update this MMR if the temperature
conversion result ready bit (ADCSTA[2]) is set.
If I-ADC and V-ADC is not active, a read of this
MMR by the MCU clears all asserted ready flags
(ADCSTA[2]). A ready of this MMR clears
ADCSTA[2].
0xFFFF0520
0xFFFF0524
0xFFFF0528
This ADC Data MMR holds the 16-bit temperature
Rev. B | Page 56 of 140
Current Channel ADC Offset Calibration Register
Name:
Address:
Default
Value:
Access:
Function:
Voltage Channel ADC Offset Calibration Register
Name:
Address:
Default
Value:
Access:
Function:
ADC0OF
0xFFFF0530
Part specific, factory programmed
Read/write access
This ADC Offset MMR holds a 16-bit offset
calibration coefficient for the I-ADC. The register
is configured at power-on with a factory default
value. However, this register automatically over-
writes if an offset calibration of the I-ADC is
initiated by the user via bits in the ADCMDE
MMR. User code can only write to this calibration
register if the ADC is in idle mode. An ADC must
be enabled and in idle mode before being written
to any offset or gain register. The ADC must be in
idle mode for at least 23 μs.
ADC1OF
0xFFFF0534
Part specific, factory programmed
Read/write access
This offset MMR holds a 16-bit offset calibration
coefficient for the voltage channel. The register is
configured at power-on with a factory default
value. However, this register is automatically
overwritten if an offset calibration of the voltage
channel is initiated by the user via bits in the
ADCMDE MMR. User code can only write to this
calibration register if the ADC is in idle mode. An
ADC must be enabled and in idle mode before
being written to any offset or gain register. The
ADC must be in idle mode for at least 23 μs.