ADUC7033BCPZ-8L Analog Devices Inc, ADUC7033BCPZ-8L Datasheet - Page 72

• Manufacturer Part Number: ADUC7033BCPZ-8L
• Description: IC MCU FLASH 96K ANLG I/O 48LFCS
• Manufacturer: Analog Devices Inc
• Type: Battery Managementr

Specifications of ADUC7033BCPZ-8L

• Input Type: Logic
• Output Type: Logic
• Interface: UART, SPI
• Current - Supply: 20mA
• Mounting Type: Surface Mount
• Package / Case: 48-LFCSP
• For Use With: EVAL-ADUC7033QSPZ - EVAL DEV QUICK START ADUC7033
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

ADuC7033
PROCESSOR REFERENCE PERIPHERALS
INTERRUPT SYSTEM
There are 17 interrupt sources on the ADuC7033 that are
controlled by the interrupt controller. Most interrupts are
generated from the on-chip peripherals such as the ADC,
UART, and so on. The ARM7TDMI CPU core only recognizes
interrupts as one of two types: a normal interrupt request (IRQ)
and a fast interrupt request (FIQ). All the interrupts can be
masked separately.
The control and configuration of the interrupt system are
managed through nine interrupt-related registers, four
dedicated to IRQ and four dedicated to FIQ. An additional
MMR is used to select the programmed interrupt source. The
bits in each IRQ and FIQ register represent the same interrupt
source as described in Table 50.
IRQSTA/FIQSTA should be saved immediately upon entering
the interrupt service routine (ISR) to ensure that all valid
interrupt sources are serviced.
The interrupt generation route through the ARM7TDMI core is
shown in Figure 31.
Table 50. IRQ/FIQ MMRs Bit Designations
Bit
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
Description
All interrupts OR’ed (FIQ only)
SWI: not used in IRQEN/CLR and FIQEN/CLR
Timer0
Timer1
Timer2 or wake-up timer
Timer3 or watchdog timer
Timer4 or STI timer
LIN hardware
Flash/EE interrupt
PLL lock
ADC
UART
SPI master
XIRQ0 (GPIO IRQ0 )
XIRQ1 (GPIO IRQ1)
Reserved—should be written as 0
IRQ3 (high voltage IRQ)
SPI slave
XIRQ4 (GPIO IRQ4)
XIRQ5 (GPIO IRQ5)
Rev. B | Page 72 of 140
Comments
See the Timer0—Lifetime Timer section.
See the Timer1 section.
See the Timer2 or Wake-Up Timer section.
See the Timer3 or Watchdog Timer section.
See the Timer4 or STI Timer section.
See the LIN (Local Interconnect Network) Interface section.
See the Flash/EE Control Interface section.
See the System Clocks section.
See the 16-Bit, Σ-Δ Analog-to-Digital Converters section.
See the UART Serial Interface section.
See the Serial Peripheral Interface section.
See the General-Purpose I/O section.
See the General-Purpose I/O section.
High Voltage Interrupt. See the High Voltage Peripheral Control
Interface section.
See the Serial Peripheral Interface section.
See the General-Purpose I/O section.
See the General-Purpose I/O section.
Consider the example of Timer0, which is configured to generate a
timeout every 1 ms. After the first 1 ms timeout, FIQSIG/IRQSIG[2]
is set and can be cleared only by writing to T0CLRI.
If Timer0 is not enabled in either IRQEN or FIQEN, then
FIQSTA/IRQSTA[2] is not set and an interrupt does not occur.
However, if Timer0 is enabled in either IRQEN or FIQEN, then
either FIQSTA/IRQSTA[2] is set or an interrupt (either an FIQ
or IRQ) occurs.
Note that the IRQ and FIQ interrupt bit definitions in the CPSR
only control interrupt recognition by the ARM core, not by the
peripherals. For example, if Timer2 is configured to generate an
IRQ via IRQEN, the IRQ interrupt bit is set (disabled) in the
CPSR and the ADuC7033 is powered down. When an interrupt
occurs, the peripherals power up, but the ARM core remains
powered down. This is equivalent to POWCON = 0x71. The
ARM core can only be powered up by a reset event if this occurs.