ADUC7033BCPZ-8L Analog Devices Inc, ADUC7033BCPZ-8L Datasheet - Page 58

• Manufacturer Part Number: ADUC7033BCPZ-8L
• Description: IC MCU FLASH 96K ANLG I/O 48LFCS
• Manufacturer: Analog Devices Inc
• Type: Battery Managementr

Specifications of ADUC7033BCPZ-8L

• Input Type: Logic
• Output Type: Logic
• Interface: UART, SPI
• Current - Supply: 20mA
• Mounting Type: Surface Mount
• Package / Case: 48-LFCSP
• For Use With: EVAL-ADUC7033QSPZ - EVAL DEV QUICK START ADUC7033
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

ADuC7033
Current Channel ADC Result Counter Limit Register
Name:
Address:
Default
Value:
Access:
Function:
Current Channel ADC Result Count Register
Name:
Address:
Default
Value:
Access:
Function:
Current Channel ADC Threshold Register
Name:
Address:
Default
Value:
Access:
Function:
ADC0RCL
0x0001
Read/write
This 16-bit MMR sets the number of conversions
required before an ADC interrupt is generated. By
default this register is set to 0x01. The ADC
counter function must be enabled via the ADC
result counter enable bit in the ADCCFG MMR.
ADC0RCV
0x0000
Read only
This 16-bit, read-only MMR holds the current
number of I-ADC conversion results. It is used in
conjunction with ADC0RCL to mask I-ADC
interrupts, generating a lower interrupt rate. When
ADC0RCV = ADC0RCL, the value in ADC0RCV
resets to 0 and recommences counting. It can also
be used in conjunction with the accumulator
(ADC0ACC) to allow an average current calculation
to be undertaken. The result counter is enabled via
ADCCFG[0]. This MMR is also reset to 0 when the
I-ADC is reconfigured, that is, when the
ADC0CON or ADCMDE are written.
ADC0TH
0x0000
Read/write
This 16-bit MMR sets the threshold against which
the absolute value of the I-ADC conversion result is
compared. In unipolar mode, ADC0TH[15:0] are
compared, and in twos complement mode,
ADC0TH[14:0] are compared.
0xFFFF0548
0xFFFF054C
0xFFFF0550
Rev. B | Page 58 of 140
Current Channel ADC Threshold Count Limit Register
Name:
Address:
Default
Value:
Access:
Function:
Current Channel ADC Threshold Count Register
Name:
Address:
Default
Value:
Access:
Function:
Current Channel ADC Accumulator Register
Name:
Address:
Default
Value:
Access:
Function:
ADC0TCL
0xFFFF0554
0x01
Read/write
This 8-bit MMR determines how many cumulative
(values below the threshold decrement or reset the
count to 0) I-ADC conversion result readings
above ADC0TH must occur before the I-ADC
comparator threshold bit is set in the ADCSTA
MMR, generating an ADC interrupt. The I-ADC
comparator threshold bit is asserted as soon as
ADC0THV = ADC0TCL.
ADC0THV
0xFFFF0558
0x00
Read only
This 8-bit MMR increments every time the absolute
value of an I-ADC conversion result |I| ≥ ADC0TH.
This register is decremented or reset to 0 every
time the absolute value of an I-ADC conversion
result |I| < ADC0TH. The configuration of this
function is enabled via the current channel ADC
comparator bits in the ADCCFG MMR.
ADC0ACC
0xFFFF055C
0x00000000
Read only
This 32-bit MMR holds the current accumulator
value. The I-ADC ready bit in the ADCSTA MMR
should be used to determine when it is safe to read
this MMR. The MMR value is reset to 0 by disabling
the accumulator in the ADCCFG MMR or reconfi-
guring the current channel ADC.