ADUC7033BCPZ-8L Analog Devices Inc, ADUC7033BCPZ-8L Datasheet - Page 28

• Manufacturer Part Number: ADUC7033BCPZ-8L
• Description: IC MCU FLASH 96K ANLG I/O 48LFCS
• Manufacturer: Analog Devices Inc
• Type: Battery Managementr

Specifications of ADUC7033BCPZ-8L

• Input Type: Logic
• Output Type: Logic
• Interface: UART, SPI
• Current - Supply: 20mA
• Mounting Type: Surface Mount
• Package / Case: 48-LFCSP
• For Use With: EVAL-ADUC7033QSPZ - EVAL DEV QUICK START ADUC7033
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

ADuC7033
Command Sequence for Executing a Mass Erase
Giving the significance of the mass erase command, a specific
code sequence must be executed to initiate this operation.
1.
2.
3.
4.
Sequence Example
The command sequence for executing a mass erase is illustrated in the following example:
Int a = FEExSTA;
FEExMOD = 0x08;
FEExADR = 0xFFC3;
FEExDAT = 0x3CFF;
FEExCON = 0x06;
while (FEExSTA & 0x04){} // Wait for command to finish
FEE0STA and FEE1STA Registers
Name:
Address:
Default Value:
Access:
Function:
Table 14. FEE0STA and FEE1STA MMR Bit Designations
Bit
7 to 4
3
2
1
0
1
x is 0 or 1 to designate Flash/EE memory Block0 or Block1.
Set Bit 3 in FEExMOD.
Write 0xFFC3 in FEExADR
Write 0x3CFF in FEExDAT
Run the Mass Erase Command 0x06 in FEExCON
Description
Not Used. These bits are not used and always read as 0.
Flash/EE Memory Interrupt Status Bit.
Set automatically when an interrupt occurs, that is, when a command is complete and the Flash/EE memory interrupt enable
bit in the FEExMOD register is set.
Cleared automatically when the FEExSTA register is read by user code.
Flash/EE Memory Controller Busy.
Set automatically when the Flash/EE memory controller is busy.
Cleared automatically when the controller is not busy.
Command Fail.
Set automatically when a command written to FEExCON completes unsuccessfully.
Cleared automatically when the FEExSTA register is read by user code.
Command Successful.
Set automatically by MCU when a command is completed successfully.
Cleared automatically when the FEE0STA register is read by user code.
FEE0STA and FEE1STA
0xFFFF0E00 and 0xFFFF0E80
0x20
Read only
These 8-bit read-only registers can be read by user code and reflect the current status of the Flash/EE memory
controllers.
1
// Ensure FEExSTA is cleared
// Mass erase command
Rev. B | Page 28 of 140
To run the mass erase command via FEE0CON, write
protection on the lower 64 kB must be disabled, that is,
FEE1HID/FEE1PRO are set to 0xFFFFFFFF. This is
accomplished by first removing the protection or erasing
the lower 64 kB first.