ADUC7033BCPZ-8L Analog Devices Inc, ADUC7033BCPZ-8L Datasheet - Page 84

• Manufacturer Part Number: ADUC7033BCPZ-8L
• Description: IC MCU FLASH 96K ANLG I/O 48LFCS
• Manufacturer: Analog Devices Inc
• Type: Battery Managementr

Specifications of ADUC7033BCPZ-8L

• Input Type: Logic
• Output Type: Logic
• Interface: UART, SPI
• Current - Supply: 20mA
• Mounting Type: Surface Mount
• Package / Case: 48-LFCSP
• For Use With: EVAL-ADUC7033QSPZ - EVAL DEV QUICK START ADUC7033
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

ADuC7033
TIMER3 OR WATCHDOG TIMER
Timer3 has two modes of operation, normal mode and
watchdog mode. The watchdog timer is used to recover
from an illegal software state. When enabled, it requires
periodic servicing to prevent it from forcing a reset of the
processor.
Normal Mode
The Timer3 in normal mode is identical to Timer0 in 16-bit
mode of operation, except for the clock source. The clock source
is the low power, 32.768 kHz oscillator scalable by a factor of 1,
16, or 256.
Timer3 reloads the value from T3LD when Timer3 overflows.
Watchdog Mode
Watchdog mode is entered by setting T3CON[5]. Timer3 decre-
ments from the timeout value present in the T3LD register until
zero. The maximum timeout is 512 seconds, using a maximum
prescaler/256 and full scale in T3LD.
User software should not configure a timeout period of less
than 30 ms. This is to avoid any conflict with Flash/EE memory
page erase cycles that require 20 ms to complete a single page
erase cycle and kernel execution.
If T3VAL reaches 0, a reset or an interrupt occurs, depending
on T3CON[1]. To avoid a reset or an interrupt event, any value
must be written to T3CLRI before T3VAL reaches zero. This
reloads the counter with T3LD and begins a new timeout period.
When watchdog mode is entered, T3LD and T3CON are
write protected. These two registers cannot be modified until
a power-on reset event resets the watchdog timer. After any
other reset event, the watchdog timer continues to count. The
watchdog timer should be configured in the initial lines of user
code to avoid an infinite loop of watchdog resets. User software
should only configure a minimum timeout period of 30 ms.
Timer3 is automatically halted during JTAG debug access and
only recommences counting after JTAG has relinquished
control of the ARM7 core. By default, Timer3 continues to
count during power-down. This can be disabled by setting Bit 0
in T3CON. It is recommended to use the default value, that is,
that the watchdog timer continues to count during power-down.
LOW POWER
32.768kHz
PRESCALER
1, 16, 256
Figure 37. Timer3 Block Diagram
Rev. B | Page 84 of 140
UP/DOWN COUNTER
16-BIT LOAD
TIMER3
VALUE
16-BIT
Timer3 Interface
The Timer3 interface consists of four MMRs.
T3CON is the configuration MMR described in Table 56.
T3LD and T3VAL are 16-bit registers (Bit 0 to Bit 15) and hold
16-bit unsigned integers. T3VAL is read only.
T3CLRI is an 8-bit register. Writing any value to this register
clears the Timer3 interrupt in normal mode or resets a new
timeout period in watchdog mode.
Timer3 Load Register
Name:
Address:
Default Value:
Access:
Function:
Timer3 Value Register
Name:
Address:
Default Value:
Access:
Function:
Timer3 Clear Register
Name:
Address:
Access:
Function:
WATCHDOG RESET
TIMER3 IRQ
T3LD
0xFFFF0360
0x0040
Read/write
This 16-bit MMR holds the Timer3
reload value.
T3VAL
0xFFFF0364
0x0040
Read only
This 16-bit, read only MMR holds the current
Timer3 count value.
T3CLRI
0xFFFF036C
Write only
This 16-bit, write-only MMR is written (with
any value) by user code to refresh (reload)
Timer3 in watchdog mode to prevent a
watchdog timer reset event.