ADUC7033BCPZ-8L Analog Devices Inc, ADUC7033BCPZ-8L Datasheet - Page 128

• Manufacturer Part Number: ADUC7033BCPZ-8L
• Description: IC MCU FLASH 96K ANLG I/O 48LFCS
• Manufacturer: Analog Devices Inc
• Type: Battery Managementr

Specifications of ADUC7033BCPZ-8L

• Input Type: Logic
• Output Type: Logic
• Interface: UART, SPI
• Current - Supply: 20mA
• Mounting Type: Surface Mount
• Package / Case: 48-LFCSP
• For Use With: EVAL-ADUC7033QSPZ - EVAL DEV QUICK START ADUC7033
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

ADuC7033
Example LIN Hardware Synchronization Routine
Consider the following C-Source Code LIN initialization routine.
void LIN_INIT(void )
{
}
Using this configuration, LHSVAL1 begins to count on the first
falling edge received on the LIN bus. If LHSVAL1 exceeds the
value written to LHSVAL1, in this case 0x3F, a break compare
interrupt is generated.
On the next falling edge, LHSVAL0 begins counting. LHSVAL0
monitors the number of falling edges and compares this to the
value written to LHSCON1[7:4]. In this example, the number of
edges to monitor is the sixth falling edge of the LIN frame, or
char HVstatus;
GPCON = 0x110000;
LHSCON0 = 0x1;
do{
while (!(HVstatus & 0x4));
while((LHSSTA & 0x20) == 0 )
{
}
LHSCON1 = 0x062;
LHSCON0 = 0x0114;
LHSVAL1 = 0x03F;
HVDAT = 0x02;
HVCON = 0x08;
}
do{
while(HVstatus & 0x1);// Wait until command is finished
}
HVstatus = HVCON;
// Enable LHS on GPIO pins
// Reset LHS interface
// Enable normal LIN TX mode
// Write to Config0
// Transmit command is correct
// Wait until the LHS hardware is reset
// Sets Stop Edge as the fifth falling edge
// and the Start Edge as the first falling
// edge in the sync byte
// Gates UART RX line, ensure no interference
// from the LIN into the UART
// Selects the stop condition as a falling edge
// Enables generation of an Interrupt on the
// stop condition
// Enables the interface
// Set number of 131 kHz periods to generate
// a break interrupt 0x3F / 131 kHz ~ 480 μs
// which is just over 9.5 tbits
Rev. B | Page 128 of 140
the fifth falling edge of the sync byte. When this number of
falling edges is received, a stop condition interrupt is generated.
It is at this point that the UART is configured to receive the
protected identifier.
The UART must not be ungated (through LHSCON0[8]) before
the LIN bus returns high. If this occurs, UART communication
errors can occur. This process is shown in detail in Figure
Example code to ensure this is as follows:
.