ADUC7033BCPZ-8L Analog Devices Inc, ADUC7033BCPZ-8L Datasheet - Page 121

• Manufacturer Part Number: ADUC7033BCPZ-8L
• Description: IC MCU FLASH 96K ANLG I/O 48LFCS
• Manufacturer: Analog Devices Inc
• Type: Battery Managementr

Specifications of ADUC7033BCPZ-8L

• Input Type: Logic
• Output Type: Logic
• Interface: UART, SPI
• Current - Supply: 20mA
• Mounting Type: Surface Mount
• Package / Case: 48-LFCSP
• For Use With: EVAL-ADUC7033QSPZ - EVAL DEV QUICK START ADUC7033
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

LIN (LOCAL INTERCONNECT NETWORK) INTERFACE
The ADuC7033 features high voltage physical interfaces
between the ARM7 MCU core and an external LIN bus. The
LIN interface operates as a slave only interface, operating from
1 kBaud to 20 kBaud, and it is compatible with the LIN 2.0
standard. The pull-up resistor required for a slave node is on-
chip, reducing the need for external circuitry. The LIN protocol
is emulated using the on-chip UART, an IRQ, a dedicated LIN
timer, and the high voltage transceiver (also incorporated on-
chip) as shown in Figure 4 . The LIN is clocked from the low
power oscillator for the break timer, and a 5 MHz output from
the PLL is used for the synchronous byte timing.
GP2DAT[29]
GP2DAT[21]
131kHz
GPIO_12
LHS INTERRUPT
5MHz
IRQEN[7]
AND
ADuC7033
ADuC7033
HARDWARE
LHSVAL0
LHSVAL1
UART
LHS
RxD ENABLE
LHSCON0[8]
GP2CON[20]
FUNCTION
RxD
TxD
SELECT
GPIO12
INTERRUPT
LOGIC
LHS
DISABLE
OUTPUT
Figure 45. LIN I/O, Block Diagram
SHORT-CIRCUIT
HVCFG0[1:0]
LIN MODE
HVCFG1[2]
CONTROL
FOUR LIN
INTERRUPT
SOURCES
BREAK LHSSTA[0]
START LHSSTA[1]
STOP LHSSTA[2]
BREAK
ERROR LHSSTA[4]
Rev. B | Page 121 of 140
INPUT
VOLTAGE
THRESHOLD
REFERENCE
BPF
TRIP REFERENCE
SHORT-CIRCUIT
INTERNAL
LIN MMR DESCRIPTION
The LIN hardware synchronization (LHS) functionality is
controlled through five MMRs. The function of each MMR is as
follows:
Table 92. LIN MMR Descriptions
MMR
Name
LHSSTA
LHSCON0
LHSCON1
LHSVAL0
LHSVAL1
VDD
PROTECTION
INTERNAL
SHORT-CIRCUIT
SENSE
RESISTOR
VOLTAGE
LIN ENABLE
(INTERNAL
HVCFG0[5]
OVER
Description
LHS Status Register. This MMR contains information
flags that describe the current status on the
interface.
LHS Control Register 0. This MMR controls the
configuration of the LHS timer.
LHS Start and Stop Edge Control Register. Dictates
which edge of the LIN synchronization byte the
LHS starts/stops counting.
LHS Synchronization 16-Bit Timer. Controlled by
LHSCON0.
LHS Break Timer Register.
PULL-UP)
EXTERNAL
IO_VSS
LIN PIN
SCR
VDD
MASTER ECU
PROTECTION
DIODE
MASTER ECU
PULL-UP
C
LOAD
ADuC7033