ADUC7033BCPZ-8L Analog Devices Inc, ADUC7033BCPZ-8L Datasheet - Page 132

• Manufacturer Part Number: ADUC7033BCPZ-8L
• Description: IC MCU FLASH 96K ANLG I/O 48LFCS
• Manufacturer: Analog Devices Inc
• Type: Battery Managementr

Specifications of ADUC7033BCPZ-8L

• Input Type: Logic
• Output Type: Logic
• Interface: UART, SPI
• Current - Supply: 20mA
• Mounting Type: Surface Mount
• Package / Case: 48-LFCSP
• For Use With: EVAL-ADUC7033QSPZ - EVAL DEV QUICK START ADUC7033
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

ADuC7033
Typical BSD Program Flow
Because BSD is a PWM communications protocol controlled by
software, it is necessary for the user to construct the required
data from each bit. For example, in constructing the slave
address, the slave node receives the three bits and the user
constructs the relevant address.
When the master initiates BSD, data is transmitted and received
by the slave node. A flow diagram showing this process is
shown in Figure 5 .
BUS PULLED LOW
BY MASTER
RECEIVE SECOND
RECEIVE DATA
FROM MASTER
t
SYNC
Figure 56. BSD Slave Node State Machine
PARITY BIT
Figure 55. BSD Slave Transmitting Zero
t
0
SYNCHRONIZATION
INITIALIZE BSD
RECEIVE FIRST
HARDWARE/
SOFTWARE
DIRECTION
PARITY BIT
ACK/NACK
REGISTER
TRANSMIT
ADDRESS
ADDRESS
RECEIVE
RECEIVE
RECEIVE
RECEIVE
PULSES
SLAVE
BIT
BUS HELD LOW
BY SLAVE
RELEASED BY
MASTER
BUS RELEASED BY
SLAVE AFTER
TRANSMIT SECOND
TRANSMIT DATA
TO MASTER
PARITY BIT
t
0
Rev. B | Page 132 of 140
BSD DATA RECEPTION
To receive data, the LIN/BSD peripheral must first be con-
figured in BSD mode where LHSCON[6] = 1. In this mode,
LHSCON0[8] should be set to ensure the LHS break timer
(see LHSVAL1 in the LIN Hardware Break Timer1 Register
section) generates an interrupt on the rising edge of the BSD bus.
The LHS break timer is cleared and starts counting on the
falling edge of the BSD bus and is subsequently stopped and
generates an interrupt on the rising edge of the BSD bus. Given
that the LHS break timer is clocked by the low power (131 kHz)
oscillator, the value in LHSVAL1 can be interpreted by user code
to determine if the received data bit is a BSD sync pulse, 0, or 1.
BSD DATA TRANSMISSION
User code forces a GPIO signal (GPIO_12) low for a specified
time to transmit data in BSD mode. In addition, user code uses
the sync timer (LHSVAL0), LHS sync capture register (LHSCAP),
and the LHS sync compare register (LHSCMP) to time how
long the BSD bus should be held low for 0 or 1 bit transmissions.
As described previously, even when the slave is transmitting, the
master always starts the bit transmission period by pulling the
BSD bus low. If BSD mode is selected (LHSCON0[6] = 1), the
LIN sync timer value is captured in LHSCAP on every falling
edge of the BSD bus. The LIN sync timer runs continuously in
BSD mode.
User code can then immediately force GPIO_12 low and reads
the captured timer value from LHSCAP. A calculation of how
many (5 MHz) clock periods should elapse before the GPIO_12
should be driven high for a 0 or 1 pulse width can be made.
This number is added to the LHSCAP value and written into
the LHSCMP register. If LHSCON0[5] is set, the sync timer,
which continues to count (being clocked by a 5 MHz clock),
eventually equals the LHSCMP value and generates an LHS
compare interrupt (LHSSTA[3]).
The response to this interrupt should be to force the GPIO_12
signal (and, therefore, the BSD bus) high. The software control
of the GPIO_12 signal along with the correct use of the LIN
synchronization timers ensures that valid 0 and 1 pulse widths
can be transmitted from the ADuC7033, as shown in Figure 5 .
Again, care needs to be taken when switching from BSD write
mode to BSD read mode, as described in LHSCON0[8].
1
LHSVAL1 CLEARED
AND STARTS COUNTING
ON THIS EDGE
BSD ‘0’ PERIOD
Figure 57. Master Transmit, Slave Read
2
LHSVAL1 STOPPED
AND GENERATES
INTERRUPT ON THIS EDGE
BSD ‘1’ PERIOD