ADUC7033BCPZ-8L Analog Devices Inc, ADUC7033BCPZ-8L Datasheet - Page 75

• Manufacturer Part Number: ADUC7033BCPZ-8L
• Description: IC MCU FLASH 96K ANLG I/O 48LFCS
• Manufacturer: Analog Devices Inc
• Type: Battery Managementr

Specifications of ADUC7033BCPZ-8L

• Input Type: Logic
• Output Type: Logic
• Interface: UART, SPI
• Current - Supply: 20mA
• Mounting Type: Surface Mount
• Package / Case: 48-LFCSP
• For Use With: EVAL-ADUC7033QSPZ - EVAL DEV QUICK START ADUC7033
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

As shown in Figure 32, the MMR logic and core timer logic
reside in separate and asynchronous clock domains. Any data
coming from the MMR core clock domain and being passed to
the internal timer domain must be synchronized to the internal
timer clock domain to ensure it is latched correctly into the core
timer clock domain. This is achieved by using two flip-flops as
shown in Figure 33 to not only synchronize but also to double
buffer the data and thereby ensuring data integrity in the timer
clock domain.
As a result of the synchronization block, while timer control
data is latched almost immediately (with the fast, core clock) in
the MMR clock domain, this data in turn will not reach the core
timer logic for at least two periods of the selected internal timer
domain clock.
OSCILLATOR
OSCILLATOR
PRECISION
ARM7TDMI
CORE CLOCK
POWER
CLOCK
AMBA
CORE
GPIO
HIGH
XTAL
LOW
DOMAIN
(F
CORE
)
AMBA
Figure 33. Synchronizer for Signals Crossing Clock Domains
UNSYNCHRONIZED
0
1
2
4
SIGNAL
INTERFACE
T0 REG
T1 REG
T2 REG
T3 REG
T4 REG
Figure 32. Timer Block Diagram
USER
MMR
Rev. B | Page 75 of 140
TARGET_CLOCK
SYNCHRONIZER
FLIP-FLOPS
TIMER BLOCK
PROGRAMMING THE TIMERS
Understanding synchronization across timer domains also
requires that the user code carefully program the timers when
stopping or starting them. The recommended code controls the
timer block when stopping and starting the timers and when
using different clock domains. This can be critical, especially if
the timers are enabled to generate an IRQ or FIQ exception. An
example using Timer2 follows.
Halting Timer2
When halting Timer2, it is recommended that the IRQEN
bit for Timer2 be masked (using IRQCLR). This prevents
unwanted IRQs from generating an interrupt in the MCU
before the T2CON control bits have been latched in the Timer2
internal logic.
IRQCLR = WAKEUP_TIMER_BIT;
T2CON = 0x00;
SYNC
SYNC
SYNC
SYNC
SYNC
T0
T1
T2
T3
T4
SYNCHRONIZED
CLOCK DOMAIN
LOW POWER
TIMER 2
SIGNAL
T0
T1
T2
T3
T4
T0IRQ
T1IRQ
T2IRQ
T3IRQ
W
T4IRQ
D
R
//Masking interrupts
//Halting the timer
ST
ADuC7033