ADUC7033BCPZ-8L Analog Devices Inc, ADUC7033BCPZ-8L Datasheet - Page 123

• Manufacturer Part Number: ADUC7033BCPZ-8L
• Description: IC MCU FLASH 96K ANLG I/O 48LFCS
• Manufacturer: Analog Devices Inc
• Type: Battery Managementr

Specifications of ADUC7033BCPZ-8L

• Input Type: Logic
• Output Type: Logic
• Interface: UART, SPI
• Current - Supply: 20mA
• Mounting Type: Surface Mount
• Package / Case: 48-LFCSP
• For Use With: EVAL-ADUC7033QSPZ - EVAL DEV QUICK START ADUC7033
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

LIN Hardware Synchronization Control Register 0
Name:
Address:
Default Value:
Access:
Function:
Table 94. LHSCON0 MMR Bit Designations
Bit
31 to 13
12
11
10
9
8
LHSCON0
0xFFFF0784
0x0000
Read/write
The LHS control register is a 32-bit register that, in conjunction with the LHSCON1 register, is used to configure the
LIN mode of operation.
Description
Reserved. These bits are reserved for future use and should be written as 0 by user software.
Rising Edge Detected Interrupt Disable.
BSD Mode.
Set to 1 to disable the rising edge detected interrupt.
Cleared to 0 to enable the break rising edge detected interrupt.
LIN Mode.
Set to 1 to enable the rising edge detected interrupt.
Cleared to 0 to disable the break rising edge detected interrupt.
Break Timer Compare Interrupt Disable.
Set to 1 to disable the break timer compare interrupt.
Cleared to 0 to enable the break timer compare interrupt.
Break Timer Error Interrupt Disable.
Set to 1 to disable the break timer error interrupt.
Cleared to 0 to enable the break timer error interrupt.
LIN Transceiver, Standalone Test Mode.
Cleared to 0 by user code to operate the LIN in normal mode, it is driven directly from the on-chip UART.
Set to 1 by user code to enable external GPIO_7 and GPIO_8 pins to drive the LIN Transceiver TxD and LIN Transceiver
RxD, respectively, independent of the UART. The functions of GPIO_7 and GPIO_8 should first be configured by user code
via the GPIO function select Bit 0 and Bit 4 in the GP2CON register.
Gate UART/BSD R/W Bit.
Set to 1 by user code to disable the internal UART RxD (receive data) by gating it high until both the break field and
subsequent LIN sync byte have been detected. This ensures the UART does not receive any spurious serial data during
break or sync field periods that have to be flushed out of the UART before valid data fields can be received.
Set to 0 by user code to enable the internal UART RxD (receive data) after the break field and subsequent LIN sync byte
have been detected so that the UART can receive the subsequent LIN data fields.
In BSD mode, LHSCON0[6] is set to 1. Because of the finite propagation delay in the BSD transmit (from the MCU to the
external pin) and receive (from the external pin to the MCU) paths, user code must not switch between BSD write and
read modes until the MCU confirms the external BSD pin is deasserted. Failure to adhere to this recommendation can
result in the generation of an inadvertent break condition interrupt after user code switches from BSD write mode to
BSD read mode. A stop condition interrupt can be used to ensure that this scenario is avoided.
In BSD read mode, this bit is set to 1 by user code to enable the generation of a break condition interrupt (LHSSTA[0]) on a
rising edge of the BSD bus. In BSD read mode, the break timer (LHSVAL1) starts counting on the falling edge and stops
counting on the rising edge. The generation of an interrupt on this rising edge allows user code to determine if a 0, 1, or
a sync pulse width has been received. It should also be noted that the break timer still generates an interrupt if the value
in the LIN break timer (LHSVAL1 read value) equals the break timer compare value (LHSVAL1 write value), and if the break
timer overflows. This configuration can be used in BSD read mode to detect fault conditions on the BSD bus.
In BSD write mode, this bit is cleared to 0 by user code to disable the generation of break condition interrupts on a rising
edge of the BSD bus (as is required in BSD read mode). In BSD write mode, the LHS compare interrupt (LHSSTA[3]) is used to
determine when the MCU should release the BSD bus when transmitting data. If the break condition interrupt was still
enabled, it would generate an unwanted interrupt as soon as the BSD bus is deasserted. As in BSD read mode, the break
timer stops counting on a rising edge, so the break timer can also be used in this mode to allow user code to confirm the
pulse width in transmitted data bits.
Rev. B | Page 123 of 140
ADuC7033