ADUC7033BCPZ-8L Analog Devices Inc, ADUC7033BCPZ-8L Datasheet - Page 73

• Manufacturer Part Number: ADUC7033BCPZ-8L
• Description: IC MCU FLASH 96K ANLG I/O 48LFCS
• Manufacturer: Analog Devices Inc
• Type: Battery Managementr

Specifications of ADUC7033BCPZ-8L

• Input Type: Logic
• Output Type: Logic
• Interface: UART, SPI
• Current - Supply: 20mA
• Mounting Type: Surface Mount
• Package / Case: 48-LFCSP
• For Use With: EVAL-ADUC7033QSPZ - EVAL DEV QUICK START ADUC7033
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

IRQ
The IRQ is the exception signal to enter the IRQ mode of the
processor. It is used to service general-purpose interrupt
handling of internal and external events.
All 32 bits are logically OR’ e d to create a single IRQ signal to
the ARM7TDMI core. The four 32-bit registers dedicated to
IRQ follow.
IRQSIG
IRQSIG reflects the status of the different IRQ sources. If a
peripheral generates an IRQ signal, the corresponding bit in
the IRQSIG is set, otherwise it is cleared. The IRQSIG bits are
cleared when the interrupt in the particular peripheral is cleared.
All IRQ sources can be masked in the IRQEN MMR. IRQSIG
is read only.
IRQEN
IRQEN provides the value of the current enable mask. When
a bit is set to 1, the corresponding source request is enabled
to create an IRQ exception. When a bit is set to 0, the corre-
sponding source request is disabled or masked, which does not
create an IRQ exception. The IRQEN register cannot be used to
disable an interrupt.
IRQCLR
IRQCLR is a write-only register that allows clearing the IRQEN
register to mask an interrupt source. Each bit set to 1 clears the
corresponding bit in the IRQEN register without affecting the
remaining bits. The pair of registers, IRQEN and IRQCLR,
allow independent manipulation of the enable mask without
requiring an atomic read-modify-write.
IRQSTA
IRQSTA is a read only register that provides the current enabled
IRQ source status (effectively a Logic AND of the IRQSIG and
IRQEN bits). When set to 1, that source generates an active IRQ
request to the ARM7TDMI core. There is no priority encoder
or interrupt vector generation. This function is implemented in
software in a common interrupt handler routine.
Fast Interrupt Request (FIQ)
The fast interrupt request (FIQ) is the exception signal to enter
the FIQ mode of the processor. It is provided to service data
transfer or communication channel tasks with low latency. The
FIQ interface is identical to the IRQ interface and provides the
second level interrupt (highest priority). Four 32-bit registers
are dedicated to FIQ: FIQSIG, FIQEN, FIQCLR, and FIQSTA.
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Bit 31 to Bit 1 of FIQSTA are logically OR’ e d to create the FIQ
signal to the core and to Bit 0 of both the FIQ and IRQ registers
(FIQ source).
The logic for FIQEN and FIQCLR does not allow an interrupt
source to be enabled in both IRQ and FIQ masks. A bit set to 1
in FIQEN clears, as a side effect, the same bit in IRQEN. Likewise,
a bit set to 1 in IRQEN clears, as a side effect, the same bit in
FIQEN. An interrupt source can be disabled in both IRQEN
and FIQEN masks.
Programmed Interrupts
Because the programmed interrupts are not maskable, they are
controlled by another register, SWICFG, that writes into both
IRQSTA and IRQSIG registers and/or the FIQSTA and FIQSIG
registers at the same time.
The 32-bit register dedicated to software interrupt is SWICFG
described in Table 51. This MMR allows the control of a
programmed source interrupt.
Table 51. SWICFG MMR Bit Designations
Bit
31 to 3
2
1
0
Note that to be detected by the interrupt controller and to be
detected by the user in the IRQSTA and FIQSTA registers, any
interrupt signal must be active for at least the minimum
interrupt latency time.
PLL LOCK
PLL LOCK
FLASH/EE
FLASH/EE
Description
Reserved.
Programmed Interrupt FIQ.
Setting/clearing this bit corresponds to
setting/clearing Bit 1 of FIQSTA and FIQSIG.
Programmed Interrupt IRQ.
Setting/clearing this bit corresponds to
setting/clearing Bit 1 of IRQSTA and IRQSIG.
Reserved.
LIN H/W
LIN H/W
TIMER0
TIMER1
TIMER2
TIMER3
TIMER0
TIMER1
TIMER2
TIMER3
UART
UART
XIRQ
XIRQ
ADC
ADC
SPI
SPI
Figure 31. Interrupt Structure
ADuC7033
IRQ
FIQ