ADUC7033BCPZ-8L Analog Devices Inc, ADUC7033BCPZ-8L Datasheet - Page 33

• Manufacturer Part Number: ADUC7033BCPZ-8L
• Description: IC MCU FLASH 96K ANLG I/O 48LFCS
• Manufacturer: Analog Devices Inc
• Type: Battery Managementr

Specifications of ADUC7033BCPZ-8L

• Input Type: Logic
• Output Type: Logic
• Interface: UART, SPI
• Current - Supply: 20mA
• Mounting Type: Surface Mount
• Package / Case: 48-LFCSP
• For Use With: EVAL-ADUC7033QSPZ - EVAL DEV QUICK START ADUC7033
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

FLASH/EE MEMORY RELIABILITY
The Flash/EE memory array on the part is fully qualified for
two key Flash/EE memory characteristics: Flash/EE memory
cycling endurance and Flash/EE memory data retention.
Endurance quantifies the ability of the Flash/EE memory to be
cycled through many program, read, and erase cycles. A single
endurance cycle is composed of four independent, sequential
events, defined as
1.
2.
3.
4.
In reliability qualification, every halfword (16-bit wide) location
of the three pages (top, middle, and bottom) in the Flash/EE
memory cycles 10,000 times from 0x0000 to 0xFFFF. As
indicated in Table 1, the Flash/EE memory endurance
qualification of the part is carried out in accordance with
JEDEC Retention Lifetime Specification A117. The results allow
the specification of a minimum endurance figure over supply
and temperature of 10,000 cycles.
Retention quantifies the ability of the Flash/EE memory to
retain its programmed data over time. Again, the part is
qualified in accordance with the formal JEDEC Retention
Lifetime Specification A117 at a specific junction temperature
(T
Flash/EE memory is cycled to its specified endurance limit,
described previously, before data retention is characterized.
This means that the Flash/EE memory is guaranteed to retain
its data for its fully specified retention lifetime every time the
Flash/EE memory is reprogrammed. Note that retention
lifetime, based on an activation energy of 0.6 eV, derates with T
as shown in Figure 14.
CODE EXECUTION TIME FROM SRAM AND
FLASH/EE
This section describes SRAM and Flash/EE access times during
execution for applications where execution time is critical.
J
= 85°C). As part of this qualification procedure, the
Initial page erase sequence.
Read/verify sequence.
Byte program sequence.
Second read/verify sequence.
600
450
300
150
0
30
Figure 14. Flash/EE Memory Data Retention
40
JUNCTION TEMPERATURE (°C)
55
70
85
100
125
135
150
Rev. B | Page 33 of 140
J
,
Execution from SRAM
Fetching instructions from SRAM takes one clock cycle because
the access time of the SRAM is 2 ns, and a clock cycle is 49 ns
minimum. However, if the instruction involves reading or writing
data to memory, one extra cycle must be added if the data is in
SRAM. If the data is in Flash/EE memory, two extra cycles are
needed to retrieve the 32-bit data from Flash/EE.
A control flow instruction (for example, a branch instruction)
takes one cycle to fetch and two cycles to fill the pipeline with the
new instructions.
Execution from Flash/EE
In Thumb mode, where instructions are 16 bits, one cycle is
needed to fetch any instruction.
In ARM mode, with CD = 0, two cycles are needed to fetch the
32-bit instructions. With CD > 0, no extra cycles are required
for the fetch because the Flash/EE memory continues to be
clocked at full speed. In addition, some dead time is needed
before accessing data for any value of CD bits.
Timing is identical in both modes when executing instructions
that involve using the Flash/EE for data memory. If the instruction
to be executed is a control flow instruction, an extra cycle is
needed to decode the new address of the program counter, and
then four cycles are needed to fill the pipeline if CD = 0.
A data processing instruction involving only the core register
does not require any extra clock cycles. Data transfer instructions
are more complex and are summarized in Table 18.
Table 18. Typical Execution Cycles in ARM/Thumb Mode
Instructions
LD
LDH
LDM/PUSH
STR
STRH
STRM/POP
With 1 < N ≤ 16, N = the number of data to load or store in the
multiple load/store instruction.
By default, Flash/EE code execution is suspended during any
Flash/EE erase or write cycle. A page (512 bytes) erase cycle
takes 20 ms and a write (16 bits) word command takes 50 μs.
However, the Flash/EE controller allows erase/write cycles to
abort if the ARM core receives an enabled interrupt during the
current Flash/EE erase/write cycle. The ARM7 can therefore
immediately service the interrupt and return to repeat the
Flash/EE command. The abort operation typically takes 10 clock
cycles. If the abort operation is not feasible, it is possible to
run Flash/EE programming code and the relevant interrupt
routines from SRAM, allowing the core to immediately service
the interrupt.
Fetch
Cycles
2/1
2/1
2/1
2/1
2/1
2/1
Dead
Time
1
1
N
1
1
N
Data Access
2
1
2 × N
2 × 50 μs
50 μs
2 × N × 50 μs
ADuC7033