ADUC7033BCPZ-8L Analog Devices Inc, ADUC7033BCPZ-8L Datasheet - Page 36

• Manufacturer Part Number: ADUC7033BCPZ-8L
• Description: IC MCU FLASH 96K ANLG I/O 48LFCS
• Manufacturer: Analog Devices Inc
• Type: Battery Managementr

Specifications of ADUC7033BCPZ-8L

• Input Type: Logic
• Output Type: Logic
• Interface: UART, SPI
• Current - Supply: 20mA
• Mounting Type: Surface Mount
• Package / Case: 48-LFCSP
• For Use With: EVAL-ADUC7033QSPZ - EVAL DEV QUICK START ADUC7033
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

ADuC7033
MEMORY MAPPED REGISTERS
The memory mapped register (MMR) space is mapped into the
top 4 kB of the MCU memory space and accessed by indirect
addressing, load, and store commands through the ARM7
banked registers. An outline of the memory mapped register
bank for the ADuC7033 is shown in Figure 16.
The MMR space provides an interface between the CPU and all
on-chip peripherals. All registers except the ARM7 core registers
(described in the ARM Registers section) reside in the MMR area.
As shown in the detailed MMR maps in the Complete MMR
Listing (Table 19 to Table 30), the MMR data widths vary from
1 byte (8 bits) to 4 bytes (32 bits). The ARM7 core can access
any of the MMRs (single byte or multiple byte width registers)
with a 32-bit read or write access.
The resulting read, for example, is aligned per little endian
format as previously the Memory Mapped Registers section and
illustrated in Figure 12. However, errors result if the ARM7 core
tries to access 4-byte (32-bit) MMRs with a 16-bit access. In the
case of a (16-bit) write access to a 32-bit MMR, the (upper) 16
most significant bits are written as 0s. More obviously, in the
case of a 16-bit read access to a 32-bit MMR, only 16 of the
MMR bits can be read.
Rev. B | Page 36 of 140
0xFFFFFFFF
0xFFFF0D50
0xFFFF0D00
0xFFFF0A14
0xFFFF0A00
0xFFFF079C
0xFFFF044C
0xFFFF0E00
0xFFFF1000
0xFFFF0894
0xFFFF0880
0xFFFF0810
0xFFFF0800
0xFFFF0780
0xFFFF0730
0xFFFF0700
0xFFFF0580
0xFFFF0500
0xFFFF0400
0xFFFF0394
0xFFFF0380
0xFFFF0370
0xFFFF0360
0xFFFF0350
0xFFFF0340
0xFFFF0334
0xFFFF0320
0xFFFF0318
0xFFFF0300
0xFFFF0244
0xFFFF0220
0xFFFF0110
0xFFFF0000
Figure 16. Top Level MMR Map
OSCILLATOR CONTROL
GENERAL-PURPOSE
GENERAL-PURPOSE
SYSTEM CONTROL
FLASH CONTROL
HV INTERFACE
CONTROLLER
SERIAL TEST
HARDWARE
WATCHDOG
REMAP AND
INTERFACE
INTERFACE
INTERRUPT
WAKE-UP
PLL AND
LIN/BSD
TIMER 4
TIMER 3
TIMER 2
TIMER 1
TIMER 0
UART
GPIO
ADC
SPI