ADUC7033BCPZ-8L Analog Devices Inc, ADUC7033BCPZ-8L Datasheet - Page 53

• Manufacturer Part Number: ADUC7033BCPZ-8L
• Description: IC MCU FLASH 96K ANLG I/O 48LFCS
• Manufacturer: Analog Devices Inc
• Type: Battery Managementr

Specifications of ADUC7033BCPZ-8L

• Input Type: Logic
• Output Type: Logic
• Interface: UART, SPI
• Current - Supply: 20mA
• Mounting Type: Surface Mount
• Package / Case: 48-LFCSP
• For Use With: EVAL-ADUC7033QSPZ - EVAL DEV QUICK START ADUC7033
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

ADC Filter Register
Name:
Address:
Default Value:
Access:
Function:
Note:
Table 39. ADCFLT MMR Bit Designations
1
2
Bit
15
14
13 to 8
7
6 to 0
Due to limitations on the digital filter internal data path, there are some limitations on the combinations of the Sinc3 decimation factor (SF) and averaging factor (AF)
that can be used to generate a required ADC output rate. This restriction limits the minimum ADC update in normal power mode to 4 Hz or 1 Hz in low power mode.
In low power mode and low power plus mode, the ADC is driven directly by the low power oscillator (131 kHz) and not 512 kHz. All f
by 4 (approx).
ADCFLT
0xFFFF0518
0x0007
Read/write
The ADC Filter MMR is a 16-bit register that controls the speed and resolution of the on-chip ADCs.
If ADCFLT is modified, the current and voltage/temperature ADCs are reset.
enabled when chopping is active. It is an optional feature when chopping is inactive, and if enabled (when chopping is
inactive) does not reduce the ADC output rate but does increase the settling time by one conversion period.
postfilter. The averaging factor can further reduce ADC noise at the expense of output rate as described in Bits[6:0], the
Sinc3 decimation factor in this table.
by approximately 5 dB. This is achieved by inserting a second notch (NOTCH2) at
Sinc3 filter. The output rate from the Sinc3 filter is given by
Description
Chop Enable. Set by the user to enable system chopping of all active ADCs. When this bit is set, the ADC has very low
offset errors and drift, but the ADC output rate is reduced by a factor of three if AF = 0 (see Sinc3 decimation factor,
Bits[6:0] in this table). If AF > 0, then the ADC output update rate is the same with chop on or off. When chop is enabled,
the settling time is two output periods.
Running Average.
Set by the user to enable a running-average-by-two function reducing ADC noise. This function is automatically
Cleared by the user to disable the running average function.
Averaging Factor (AF). The values written to these bits are used to implement a programmable first-order Sinc3
Sinc3 Modify. Set by the user to modify the standard Sinc3 frequency response to increase the filter stop band rejection
f
where f
Sinc3 Decimation Factor (SF)
f
when the chop bit (Bit 15, chop enable) = 0 and the averaging factor (AF) = 0. This is valid for all SF values ≤ 125.
For SF = 126, f
For SF = 127, f
For information on calculating the f
NOTCH2
ADC
= (512,000/([SF + 1] × 64)) Hz
= 1.333 × f
NOTCH
is the location of the first notch in the response.
ADC
ADC
NOTCH
is forced to 60 Hz.
is forced to 50 Hz.
1
.The value (SF) written in these bits controls the oversampling (decimation factor) of the
2
ADC
for SF (other than 126 and 127) and AF values, refer to Table 40.
Rev. B | Page 53 of 140
ADC
calculations should be divided
ADuC7033