DSPD56367PV150 Freescale Semiconductor, DSPD56367PV150 Datasheet - Page 10

• Manufacturer Part Number: DSPD56367PV150
• Manufacturer: Freescale Semiconductor

Specifications of DSPD56367PV150

• Device Core Size: 24b
• Format: Fixed Point
• Clock Freq (max): 150MHz
• Mips: 150
• Device Input Clock Speed: 150MHz
• Ram Size: 69KB
• Program Memory Size: 120KB
• Operating Supply Voltage (typ): 1.8/3.3V
• Operating Supply Voltage (min): 1.71/3.14V
• Operating Supply Voltage (max): 1.89/3.46V
• Operating Temp Range: -40C to 95C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 144
• Package Type: LQFP
• Lead Free Status / Rohs Status: Not Compliant

Interrupt and Mode Control
2.9
The interrupt and mode control signals select the chip’s operating mode as it comes out of hardware reset.
After RESET is deasserted, these inputs are hardware interrupt request lines.
2-6
Signal Name
BG
BR
BB
Interrupt and Mode Control
Output
Output
Input/
Type
Input
State During
Ignored Input Bus Grant—BG is an active-low input. BG is asserted by an external bus arbitration
(deasserted)
Output
Reset
Input
Table 2-7 External Bus Control Signals (continued)
Bus Request—BR is an active-low output, never tri-stated. BR is asserted when the
DSP requests bus mastership. BR is deasserted when the DSP no longer needs the
bus. BR may be asserted or deasserted independent of whether the DSP56367 is a
bus master or a bus slave. Bus “parking” allows BR to be deasserted even though the
DSP56367 is the bus master. (See the description of bus “parking” in the BB signal
description.) The bus request hold (BRH) bit in the BCR allows BR to be asserted under
software control even though the DSP does not need the bus. BR is typically sent to an
external bus arbitrator that controls the priority, parking, and tenure of each master on
the same external bus. BR is only affected by DSP requests for the external bus, never
for the internal bus. During hardware reset, BR is deasserted and the arbitration is reset
to the bus slave state.
circuit when the DSP56367 becomes the next bus master. When BG is asserted, the
DSP56367 must wait until BB is deasserted before taking bus mastership. When BG is
deasserted, bus mastership is typically given up at the end of the current bus cycle.
This may occur in the middle of an instruction that requires more than one external bus
cycle for execution.
For proper BG operation, the asynchronous bus arbitration enable bit (ABE) in the
OMR register must be set.
Bus Busy—BB is a bidirectional active-low input/output. BB indicates that the bus is
active. Only after BB is deasserted can the pending bus master become the bus master
(and then assert the signal again). The bus master may keep BB asserted after ceasing
bus activity regardless of whether BR is asserted or deasserted. This is called “bus
parking” and allows the current bus master to reuse the bus without rearbitration until
another device requires the bus. The deassertion of BB is done by an “active pull-up”
method (i.e., BB is driven high and then released and held high by an external pull-up
resistor).
For proper BB operation, the asynchronous bus arbitration enable bit (ABE) in the OMR
register must be set.
BB requires an external pull-up resistor.
DSP56367 Technical Data, Rev. 2.1
Signal Description
Freescale Semiconductor