DSPD56367PV150 Freescale Semiconductor, DSPD56367PV150 Datasheet - Page 8

• Manufacturer Part Number: DSPD56367PV150
• Manufacturer: Freescale Semiconductor

Specifications of DSPD56367PV150

• Device Core Size: 24b
• Format: Fixed Point
• Clock Freq (max): 150MHz
• Mips: 150
• Device Input Clock Speed: 150MHz
• Ram Size: 69KB
• Program Memory Size: 120KB
• Operating Supply Voltage (typ): 1.8/3.3V
• Operating Supply Voltage (min): 1.71/3.14V
• Operating Supply Voltage (max): 1.89/3.46V
• Operating Temp Range: -40C to 95C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 144
• Package Type: LQFP
• Lead Free Status / Rohs Status: Not Compliant

Clock and PLL
2.4
2.5
When the DSP56367 enters a low-power standby mode (stop or wait), it releases bus mastership and
tri-states the relevant port A signals: A0–A17, D0–D23, AA0/RAS0–AA2/RAS2, RD, WR, BB, CAS.
2.6
2-4
Signal Name
Signal Name
Ground Name
PINIT/NMI
A0–A17
GND
GND
EXTAL
PCAP
GND
C
S
H
(2)
(2)
Clock and PLL
External Memory Expansion Port (Port A)
External Address Bus
Output
Type
Input
Bus Control Ground—GND
tied externally to all other chip ground connections. The user must provide adequate external decoupling
capacitors. There are two GND
Host Ground—GND
to all other chip ground connections. The user must provide adequate external decoupling capacitors. There
is one GND
SHI, ESAI, ESAI_1, DAX and Timer Ground—GND
and Timer. This connection must be tied externally to all other chip ground connections. The user must
provide adequate external decoupling capacitors. There are two GND
Input
Input
Type
State During
State During
Tri-Stated
H
Reset
Input
Input
Input
Reset
connection.
h
Table 2-5 External Address Bus Signals
is an isolated ground for the HD08 I/O drivers. This connection must be tied externally
External Clock Input—An external clock source must be connected to EXTAL in
order to supply the clock to the internal clock generator and PLL.
PLL Capacitor—PCAP is an input connecting an off-chip capacitor to the PLL filter.
Connect one capacitor terminal to PCAP and the other terminal to V
If the PLL is not used, PCAP may be tied to V
PLL Initial/Nonmaskable Interrupt—During assertion of RESET, the value of
PINIT/NMI is written into the PLL Enable (PEN) bit of the PLL control register,
determining whether the PLL is enabled or disabled. After RESET de assertion and
during normal instruction processing, the PINIT/NMI Schmitt-trigger input is a
negative-edge-triggered nonmaskable interrupt (NMI) request internally synchronized
to internal system clock.
Address Bus—When the DSP is the bus master, A0–A17 are active-high outputs
that specify the address for external program and data memory accesses. Otherwise,
the signals are tri-stated. To minimize power dissipation, A0–A17 do not change state
when external memory spaces are not being accessed.
Table 2-4 Clock and PLL Signals
Table 2-3 Grounds (continued)
DSP56367 Technical Data, Rev. 2.1
C
is an isolated ground for the bus control I/O drivers. This connection must be
C
connections.
Description
S
is an isolated ground for the SHI, ESAI, ESAI_1, DAX
Signal Description
Signal Description
CC
S
connections.
, GND, or left floating.
Freescale Semiconductor
CCP
.