DSPD56367PV150 Freescale Semiconductor, DSPD56367PV150 Datasheet - Page 2

• Manufacturer Part Number: DSPD56367PV150
• Manufacturer: Freescale Semiconductor

Specifications of DSPD56367PV150

• Device Core Size: 24b
• Format: Fixed Point
• Clock Freq (max): 150MHz
• Mips: 150
• Device Input Clock Speed: 150MHz
• Ram Size: 69KB
• Program Memory Size: 120KB
• Operating Supply Voltage (typ): 1.8/3.3V
• Operating Supply Voltage (min): 1.71/3.14V
• Operating Supply Voltage (max): 1.89/3.46V
• Operating Temp Range: -40C to 95C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 144
• Package Type: LQFP
• Lead Free Status / Rohs Status: Not Compliant

Overview
1-2
This data sheet uses the following conventions:
Note:
TRIPLE
TIMER
“deasserted”
Examples:
OVERBAR
“asserted”
*Values for V
1
GENERATOR
INTERFACE
PINIT/NMI
(SPDIF Tx.)
INTERNAL
CLOCK
SIX CHANNELS
SWITCH
PLL
GENERATION
RESET
DAX
DATA
DMA UNIT
BUS
ADDRESS
EXTAL
IL
UNIT
2
, V
Used to indicate a signal that is active when pulled low (For example, the RESET pin is active
when low.)
Means that a high true (active high) signal is high or that a low true (active low) signal is low
Means that a high true (active high) signal is low or that a low true (active low) signal is high
OL
Signal/Symbol
INTER-
, V
HOST
FACE
CONTROLLER
INTERRUPT
PROGRAM
IH
16
PIN
PIN
PIN
PIN
, and V
Figure 1-1 DSP56367 Block Diagram
INTER-
FACE
ESAI
EXPANSION AREA
8
OH
ESAI_1
DSP56367 Technical Data, Rev. 2.1
DSP56300
CONTROLLE
PROGRAM
MODD/IRQD
MODA/IRQA
MODB/IRQB
MODC/IRQC
are defined by individual product specifications.
24-BIT
DECODE
PERIPHERAL
4
Core
Data Sheet Conventions
6
INTER-
FACE
SHI
Logic State
GENERATOR
5
False
False
PROGRAM
ADDRESS
True
True
/INSTR. CACHE
Bootstrap ROM
PROGRAM
PROGRAM
40K x 24
192 x 24
3K x 24
ROM
RAM
MEMORY EXPANSION AREA
DDB
YDB
XDB
PDB
GDB
TWO 56-BIT ACCUMULATORS
DAB
YAB
XAB
PAB
24X24 + 56 -> 56-BIT MAC
BARREL SHIFTER
MEMORY
Signal State
13K X 24
32K x 24
DATA ALU
Deasserted
Deasserted
Asserted
RAM
ROM
Asserted
X
24 BITS BUS
MEMORY
7K X 24
8K x 24
ROM
RAM
Y
INTERFACE
SRAM BUS
EXTERNAL
ADDRESS
EXTERNAL
DATA BUS
I - CACHE
MNGMNT
SWITCH
DRAM &
SWITCH
POWER
OnCE™
JTAG
BUS
Freescale Semiconductor
&
V
V
Voltage*
V
V
IH
IH
IL
IL
/ V
/ V
/ V
/ V
CONTROL
ADDRESS
DATA
4
18
10
24
OL
OH
OH
OL