DSPD56367PV150 Freescale Semiconductor, DSPD56367PV150 Datasheet - Page 42

• Manufacturer Part Number: DSPD56367PV150
• Manufacturer: Freescale Semiconductor

Specifications of DSPD56367PV150

• Device Core Size: 24b
• Format: Fixed Point
• Clock Freq (max): 150MHz
• Mips: 150
• Device Input Clock Speed: 150MHz
• Ram Size: 69KB
• Program Memory Size: 120KB
• Operating Supply Voltage (typ): 1.8/3.3V
• Operating Supply Voltage (min): 1.71/3.14V
• Operating Supply Voltage (max): 1.89/3.46V
• Operating Temp Range: -40C to 95C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 144
• Package Type: LQFP
• Lead Free Status / Rohs Status: Not Compliant

External Memory Expansion Port (Port A)
3-18
1
2
3
4
5
6
No.
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
The number of wait states for Page mode access is specified in the DCR.
The refresh period is specified in the DCR.
The asynchronous delays specified in the expressions are valid for DSP56367.
All the timings are calculated for the worst case. Some of the timings are better for specific cases (for example, t
3 × T
value listed, as appropriate.
BRW[1–0] (DRAM control register bits) defines the number of wait states that should be inserted in each DRAM out-of-page
access.
RD deassertion always occurs after CAS deassertion; therefore, the restricted timing is t
C
CAS assertion to column address not valid
Last column address valid to RAS deassertion
WR deassertion to CAS assertion
CAS deassertion to WR assertion
CAS assertion to WR deassertion
WR assertion pulse width
Last WR assertion to RAS deassertion
WR assertion to CAS deassertion
Data valid to CAS assertion (write)
CAS assertion to data not valid (write)
WR assertion to CAS assertion
Last RD assertion to RAS deassertion
RD assertion to data valid
RD deassertion to data not valid
WR assertion to data active
WR deassertion to data high impedance
for read-after-read or write-after-write sequences). An expressions is used to calculate the maximum or minimum
Table 3-10 DRAM Page Mode Timings, Four Wait States
Characteristics
6
DSP56367 Technical Data, Rev. 2.1
Symbol
t
t
t
t
t
t
t
t
t
WCH
t
WCS
CAH
RCS
RCH
RWL
CWL
t
ROH
t
RAL
t
t
WP
DH
GA
DS
GZ
1.25 × T
1.25 × T
3.25 × T
4.75 × T
3.75 × T
1.25 × T
3.25 × T
0.75 × T
0.5 × T
3.5 × T
4.5 × T
3.5 × T
4.5 × T
Expression
5 × T
0.25 × T
1, 2, 3
C
OFF
C
C
C
C
C
C
C
C
C
C
C
C
C
− 4.0
− 4.0
− 4.5
– 4.5
− 4.0
− 4.0
(continued)
− 4.0
– 3.7
− 4.2
− 4.3
− 4.3
− 4.3
− 5.7
– 1.5
C
and not t
4
Freescale Semiconductor
GZ
31.0
46.0
28.3
40.5
43.2
33.2
31.0
41.0
Min
8.5
8.8
0.5
8.2
0.0
6.0
—
—
100 MHz
.
Max
26.8
2.5
—
—
—
—
—
—
—
—
—
—
—
—
—
—
PC
equals
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns