DSPD56367PV150 Freescale Semiconductor, DSPD56367PV150 Datasheet - Page 41

• Manufacturer Part Number: DSPD56367PV150
• Manufacturer: Freescale Semiconductor

Specifications of DSPD56367PV150

• Device Core Size: 24b
• Format: Fixed Point
• Clock Freq (max): 150MHz
• Mips: 150
• Device Input Clock Speed: 150MHz
• Ram Size: 69KB
• Program Memory Size: 120KB
• Operating Supply Voltage (typ): 1.8/3.3V
• Operating Supply Voltage (min): 1.71/3.14V
• Operating Supply Voltage (max): 1.89/3.46V
• Operating Temp Range: -40C to 95C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 144
• Package Type: LQFP
• Lead Free Status / Rohs Status: Not Compliant

Freescale Semiconductor
1
2
3
4
5
6
153
154
155
156
No.
No.
131
132
133
134
135
136
137
138
139
140
The number of wait states for Page mode access is specified in the DCR.
The refresh period is specified in the DCR.
The asynchronous delays specified in the expressions are valid for DSP56367.
All the timings are calculated for the worst case. Some of the timings are better for specific cases (e.g., t
read-after-read or write-after-write sequences).
BRW[1:0] (DRAM control register bits) defines the number of wait states that should be inserted in each DRAM out-of
page-access.
RD deassertion will always occur after CAS deassertion; therefore, the restricted timing is t
RD assertion to data valid
RD deassertion to data not valid
WR assertion to data active
WR deassertion to data high impedance
Page mode cycle time for two consecutive accesses of the
same direction
Page mode cycle time for mixed (read and write) accesses
CAS assertion to data valid (read)
Column address valid to data valid (read)
CAS deassertion to data not valid (read hold time)
Last CAS assertion to RAS deassertion
Previous CAS deassertion to RAS deassertion
CAS assertion pulse width
Last CAS deassertion to RAS assertion
CAS deassertion pulse width
Column address valid to CAS assertion
• BRW[1–0] = 00, 01—Not applicable
• BRW[1–0] = 10
• BRW[1–0] = 11
Table 3-9 DRAM Page Mode Timings, Three Wait States
Table 3-10 DRAM Page Mode Timings, Four Wait States
Characteristics
Characteristics
6
DSP56367 Technical Data, Rev. 2.1
5
Symbol
t
t
t
RHCP
t
t
t
t
RSH
CRP
t
CAC
t
OFF
CAS
t
ASC
PC
AA
CP
Symbol
t
t
GA
GZ
External Memory Expansion Port (Port A)
2.75 × T
3.75 × T
5.25 × T
7.25 × T
3.5 × T
2.5 × T
Expression
6 × T
2 × T
0.75 × T
4.5 × T
T
Expression
2.5 × T
5 × T
1, 2, 3 (continued)
C
0.25 × T
—
C
C
− 4.0
C
C
C
C
C
C
− 4.0
− 4.0
C
OFF
− 4.0
− 4.0
− 5.7
− 5.7
− 6.0
− 6.0
1, 2, 3
C
C
C
− 7.0
4
− 0.3
and not t
C
4
50.0
45.0
31.0
56.0
21.0
46.5
66.5
16.0
Min
0.0
6.0
Min
—
—
—
0.0
7.2
PC
—
—
100 MHz
GZ
100 MHz
equals 4 × TC for
.
Max
21.8
31.8
Max
18.0
2.5
—
—
—
—
—
—
—
—
—
—
—
—
—
Unit
Unit
ns
ns
ns
ns
ns
ns
ns
—
ns
ns
ns
ns
ns
ns
ns
ns
3-17