DSPD56367PV150 Freescale Semiconductor, DSPD56367PV150 Datasheet - Page 48

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DSPD56367PV150

Manufacturer Part Number
DSPD56367PV150
Description
Manufacturer
Freescale Semiconductor
Datasheet

Specifications of DSPD56367PV150

Device Core Size
24b
Format
Fixed Point
Clock Freq (max)
150MHz
Mips
150
Device Input Clock Speed
150MHz
Ram Size
69KB
Program Memory Size
120KB
Operating Supply Voltage (typ)
1.8/3.3V
Operating Supply Voltage (min)
1.71/3.14V
Operating Supply Voltage (max)
1.89/3.46V
Operating Temp Range
-40C to 95C
Operating Temperature Classification
Industrial
Mounting
Surface Mount
Pin Count
144
Package Type
LQFP
Lead Free Status / Rohs Status
Not Compliant

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
DSPD56367PV150
Manufacturer:
MOT
Quantity:
60
Part Number:
DSPD56367PV150K41R
Manufacturer:
DSP
Quantity:
59
External Memory Expansion Port (Port A)
3-24
1
2
3
4
5
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
No.
The number of wait states for out-of-page access is specified in the DCR.
The refresh period is specified in the DCR.
The asynchronous delays specified in the expressions are valid for DSP56367.
Either t
RD deassertion will always occur after CAS deassertion; therefore, the restricted timing is t
Column address valid to CAS assertion
CAS assertion to column address not valid
RAS assertion to column address not valid
Column address valid to RAS deassertion
WR deassertion to CAS assertion
CAS deassertion to WR
RAS deassertion to WR
CAS assertion to WR deassertion
RAS assertion to WR deassertion
WR assertion pulse width
WR assertion to RAS deassertion
WR assertion to CAS deassertion
Data valid to CAS assertion (write)
CAS assertion to data not valid (write)
RAS assertion to data not valid (write)
WR assertion to CAS assertion
CAS assertion to RAS assertion (refresh)
RAS deassertion to CAS assertion (refresh)
RD assertion to RAS deassertion
RD assertion to data valid
RD deassertion to data not valid
WR assertion to data active
WR deassertion to data high impedance
Table 3-12 DRAM Out-of-Page and Refresh Timings, Eleven Wait States
RCH
or t
RRH
must be satisfied for read cycles.
Characteristics
4
4
assertion
assertion
5
DSP56367 Technical Data, Rev. 2.1
Symbol
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
WCH
WCR
t
RWL
CWL
WCS
ROH
ASC
CAH
t
RCS
RCH
RRH
t
t
DHR
CSR
RPC
t
t
RAL
WP
AR
DS
DH
GA
GZ
11.75 × T
10.25 × T
0.75 × T
0.75 × T
5.25 × T
7.75 × T
1.75 × T
0.25 × T
11.5 × T
5.75 × T
5.25 × T
7.75 × T
2.75 × T
11.5 × T
3.0 × T
7.5 × T
6.5 × T
1.5 × T
10 × T
Expression
6 × T
5 × T
0.25 × T
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
− 4.0
− 4.2
C
C
− 7.0
− 4.0
− 4.2
− 4.3
− 4.0
− 4.0
− 4.0
− 4.0
− 4.0
− 2.0
− 4.5
− 4.0
− 4.0
− 4.0
− 4.0
− 4.0
− 0.3
− 4.3
− 4.3
C
OFF
1, 2, 3
and not t
Freescale Semiconductor
110.5
113.2
103.2
111.0
48.5
73.5
56.0
26.0
13.5
45.8
70.8
53.5
48.5
73.5
60.7
11.0
23.5
Min
3.5
0.5
0.0
7.2
(continued)
100 MHz
GZ
.
Max
93.0
2.5
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns

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