DSPD56367PV150 Freescale Semiconductor, DSPD56367PV150 Datasheet - Page 32

no-image

DSPD56367PV150

Manufacturer Part Number
DSPD56367PV150
Description
Manufacturer
Freescale Semiconductor
Datasheet

Specifications of DSPD56367PV150

Device Core Size
24b
Format
Fixed Point
Clock Freq (max)
150MHz
Mips
150
Device Input Clock Speed
150MHz
Ram Size
69KB
Program Memory Size
120KB
Operating Supply Voltage (typ)
1.8/3.3V
Operating Supply Voltage (min)
1.71/3.14V
Operating Supply Voltage (max)
1.89/3.46V
Operating Temp Range
-40C to 95C
Operating Temperature Classification
Industrial
Mounting
Surface Mount
Pin Count
144
Package Type
LQFP
Lead Free Status / Rohs Status
Not Compliant

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
DSPD56367PV150
Manufacturer:
MOT
Quantity:
60
Part Number:
DSPD56367PV150K41R
Manufacturer:
DSP
Quantity:
59
Reset, Stop, Mode Select, and Interrupt Timing
3-8
No.
21
22
23
24
25
26
27
Delay from WR assertion to interrupt request deassertion for
level sensitive fast interrupts
Synchronous int setup time from IRQs NMI assertion to the
CLKOUT trans.
Synch. int delay time from the CLKOUT trans2 to the first
external address out valid caused by first inst fetch
Duration for IRQA assertion to recover from Stop state
Delay from IRQA assertion to fetch of first instruction (when
exiting Stop)
Duration of level sensitive IRQA assertion to ensure interrupt
service (when exiting Stop)
Interrupt Requests Rate
• DRAM for all WS
• SRAM WS = 1
• SRAM WS = 2, 3
• SRAM WS ≥ 4
• Minimum
• Maximum
• PLL is not active during Stop (PCTL Bit 17 = 0) and Stop
• PLL is not active during Stop (PCTL Bit 17 = 0) and Stop
• PLL is active during Stop (PCTL Bit 17 = 1) (Implies No
• PLL is not active during Stop (PCTL Bit 17 = 0) and Stop
• PLL is not active during Stop (PCTL Bit 17 = 0) and Stop
• PLL is active during Stop (PCTL Bit 17 = 1) (implies no
• HDI08, ESAI, ESAI_1, SHI, DAX, Timer
• DMA
• IRQ, NMI (edge trigger)
• IRQ (level trigger)
delay is enabled (OMR Bit 6 = 0)
delay is not enabled (OMR Bit 6 = 1)
Stop Delay)
delay is enabled (OMR Bit 6 = 0)
delay is not enabled (OMR Bit 6 = 1)
Stop delay)
Table 3-7 Reset, Stop, Mode Select, and Interrupt Timing
2, 8
Characteristics
2, 8
5, 6, 7
DSP56367 Technical Data, Rev. 2.1
PLC × ET
PLC × ET
PLC × ET
PLC × ET
(WS + 3.5) × T
24.75 × T
(8.25 ± 0.5) × T
1.75 × T
2.75 × T
9.25 × T
0.6 × T
0.6 × T
− PLC/2) × T
− PLC/2) × T
+/- 0.5) × T
+/- 0.5) × T
Expression
5.5 × T
C
C
C
C
12T
12T
× PDF + (128 K
× PDF + (128 K
× PDF + (23.75
8T
8T
N/A
× PDF + (20.5
C
C
C
C
C
C
C
C
C
C
− 0.1
– 0.1
C
– 4.0
– 4.0
+ 1.0
C
+ 5.0
– 10.94
C
C
1
C
C
C
(continued)
62.7
51.7
36.7
Min
Freescale Semiconductor
3.9
3.9
Note 8
Note 8
Note 8
Note 8
170.0
Max
58.3
80.0
53.0
53.0
80.0
Unit
ms
ms
ms
ms
ns
ns
ns
ns
ns
ns
ns

Related parts for DSPD56367PV150