DSPD56367PV150 Freescale Semiconductor, DSPD56367PV150 Datasheet - Page 20

• Manufacturer Part Number: DSPD56367PV150
• Manufacturer: Freescale Semiconductor

Specifications of DSPD56367PV150

• Device Core Size: 24b
• Format: Fixed Point
• Clock Freq (max): 150MHz
• Mips: 150
• Device Input Clock Speed: 150MHz
• Ram Size: 69KB
• Program Memory Size: 120KB
• Operating Supply Voltage (typ): 1.8/3.3V
• Operating Supply Voltage (min): 1.71/3.14V
• Operating Supply Voltage (max): 1.89/3.46V
• Operating Temp Range: -40C to 95C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 144
• Package Type: LQFP
• Lead Free Status / Rohs Status: Not Compliant

Enhanced Serial Audio Interface_1
2.13
2-16
SDO0_1
FSR_1
Signal
SDO0/
Signal
FST_1
Name
PC11/
Name
PE11
PE1
PE4
Enhanced Serial Audio Interface_1
Input, Output, or
Input, Output, or
Input, Output, or
Input or Output
Input or Output
Disconnected
Disconnected
Disconnected
Signal Type
Signal Type
Output
Table 2-11 Enhanced Serial Audio Interface Signals (continued)
Table 2-12 Enhanced Serial Audio Interface_1 Signals
Disconnected
Disconnected
Disconnected
State during
State during
Reset
Reset
GPIO
GPIO
GPIO
DSP56367 Technical Data, Rev. 2.1
Serial Data Output 0—SDO0 is used to transmit data from the TX0 serial
transmit shift register.
When enabled for ESAI_1 operation, this is the ESAI_1 Serial Data Output 0.
Port C 11—When the ESAI is configured as GPIO, this signal is individually
programmable as input, output, or internally disconnected.
When enabled for ESAI_1 GPIO, this is the Port E 11 signal.
The default state after reset is GPIO disconnected.
This input is 3.3V tolerant.
Frame Sync for Receiver_1—This is the receiver frame sync input/output
signal. In the asynchronous mode (SYN=0), the FSR pin operates as the
frame sync input or output used by all the enabled receivers. In the
synchronous mode (SYN=1), it operates as either the serial flag 1 pin
(TEBE=0), or as the transmitter external buffer enable control (TEBE=1,
RFSD=1).
When this pin is configured as serial flag pin, its direction is determined by the
RFSD bit in the RCCR register. When configured as the output flag OF1, this
pin will reflect the value of the OF1 bit in the SAICR register, and the data in
the OF1 bit will show up at the pin synchronized to the frame sync in normal
mode or the slot in network mode. When configured as the input flag IF1, the
data value at the pin will be stored in the IF1 bit in the SAISR register,
synchronized by the frame sync in normal mode or the slot in network mode.
Port E 1—When the ESAI is configured as GPIO, this signal is individually
programmable as input, output, or internally disconnected.
The default state after reset is GPIO disconnected.
This input cannot tolerate 3.3V.
Frame Sync for Transmitter_1—This is the transmitter frame sync
input/output signal. For synchronous mode, this signal is the frame sync for
both transmitters and receivers. For asynchronous mode, FST is the frame
sync for the transmitters only. The direction is determined by the transmitter
frame sync direction (TFSD) bit in the ESAI transmit clock control register
(TCCR).
Port E 4—When the ESAI is configured as GPIO, this signal is individually
programmable as input, output, or internally disconnected.
The default state after reset is GPIO disconnected.
This input cannot tolerate 3.3V.
Signal Description
Signal Description
Freescale Semiconductor