DSPD56367PV150 Freescale Semiconductor, DSPD56367PV150 Datasheet - Page 68

• Manufacturer Part Number: DSPD56367PV150
• Manufacturer: Freescale Semiconductor

Specifications of DSPD56367PV150

• Device Core Size: 24b
• Format: Fixed Point
• Clock Freq (max): 150MHz
• Mips: 150
• Device Input Clock Speed: 150MHz
• Ram Size: 69KB
• Program Memory Size: 120KB
• Operating Supply Voltage (typ): 1.8/3.3V
• Operating Supply Voltage (min): 1.71/3.14V
• Operating Supply Voltage (max): 1.89/3.46V
• Operating Temp Range: -40C to 95C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 144
• Package Type: LQFP
• Lead Free Status / Rohs Status: Not Compliant

Serial Host Interface (SHI) I
3.13.1
The programmed serial clock cycle, T
HCKR (SHI clock control register).
The expression for T
where
In I
to
The programmed serial clock cycle (T
in order to achieve the desired SCL serial clock cycle (T
EXAMPLE:
For DSP clock frequency of 100 MHz (i.e. T
(F
Choosing HRS = 0 gives
Thus the HDM[7:0] value should be programmed to $36 (=54).
The resulting T
3-44
SCL
2
C mode, the user may select a value for the programmed serial clock cycle from
= 100 kHz (i.e. T
HRS is the prescaler rate select bit. When HRS is cleared, the fixed divide-by-eight prescaler is
operational. When HRS is set, the prescaler is bypassed.
HDM[7:0] are the divider modulus select bits. A divide ratio from 1 to 256
(HDM[7:0] = $00 to $FF) may be selected.
Programming the Serial Clock
I
2
CCP
T
I
will be:
Table 3-18 SCL Serial Clock Cycle (T
I
Filters bypassed
Narrow filters enabled
Wide filters enabled
2
T
CCP
2
T
CCP
SCL
I
2
I
2
C Protocol Timing
2
CCP
T
HDM 7 0 :
CCP
is
I
4096 T
2
= 10µs), T
=
CCP
6
=
[
T
=
×
[
T
I
×
[
2
T
C
10µs 2.5 10ns
=
T
CCP
C
×
C
]
[
(
C
DSP56367 Technical Data, Rev. 2.1
I
I
10ns 2
2
if HDM 7 0 :
×
2
2
R
(
=
CCP
CCP
if HDM 7 0 :
×
–
=
2
= 1000ns), with wide filters enabled:
(
( DM 7 0 :
×
8752ns
, is specified by the value of the HDM[7:0] and HRS bits of the
[
H
), SCL rise time (T
×
10
( DM 7 0 :
C
H
×
ns 2
[
= 10ns), operating in a standard mode I
×
[
[
(
×
)
54
]
[
⁄
T
T
T
2 (
=
]
I
I
I
–
×
2
2
2
+
]
CCP + 2.5
CCP + 2.5
CCP + 2.5
=
223ns 1000ns
+
$
54
×
1 )
]
02 and HRS
SCL
$
1 )
+
10ns
FF and HRS
SCL
×
×
1 )
), as shown in
×
8 ]
7 (
R
) Generated as Master
–
7 (
×
), and the filters selected should be chosen
×
×
×
×
=
×
(
T
T
T
8 ) 1
×
7
1 (
8640ns
C
C
C
×
1 (
+ 45ns +
+ 135ns +
+ 223ns +
–
–
1 (
=
–
0 )
=
=
HRS )
=
–
1
+
)
0 )
Table
8752ns
53.7
0
T
1 )
)
T
T
R
+
R
R
]
+
1
3-18.
)
1 )
]
Freescale Semiconductor
]
2
C environment