DSPD56367PV150 Freescale Semiconductor, DSPD56367PV150 Datasheet - Page 89

• Manufacturer Part Number: DSPD56367PV150
• Manufacturer: Freescale Semiconductor

Specifications of DSPD56367PV150

• Device Core Size: 24b
• Format: Fixed Point
• Clock Freq (max): 150MHz
• Mips: 150
• Device Input Clock Speed: 150MHz
• Ram Size: 69KB
• Program Memory Size: 120KB
• Operating Supply Voltage (typ): 1.8/3.3V
• Operating Supply Voltage (min): 1.71/3.14V
• Operating Supply Voltage (max): 1.89/3.46V
• Operating Temp Range: -40C to 95C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 144
• Package Type: LQFP
• Lead Free Status / Rohs Status: Not Compliant

5.3
Power dissipation is a key issue in portable DSP applications. Some of the factors which affect current
consumption are described in this section. Most of the current consumed by CMOS devices is alternating
current (ac), which is charging and discharging the capacitances of the pins and internal nodes.
Current consumption is described by the following formula:
where:
The maximum internal current (I
on best-case operation conditions, which is not necessarily a real application case. The typical internal
current (I
For applications that require very low current consumption, do the following:
Freescale Semiconductor
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Consider all device loads as well as parasitic capacitance due to PCB traces when calculating
capacitance. This is especially critical in systems with higher capacitive loads that could create
higher transient currents in the V
All inputs must be terminated (i.e., not allowed to float) using CMOS levels, except for the three
pins with internal pull-up resistors (TMS, TDI, TCK).
Take special care to minimize noise levels on the V
If multiple DSP56367 devices are on the same board, check for cross-talk or excessive spikes on
the supplies due to synchronous operation of the devices.
RESET must be asserted when the chip is powered up. A stable EXTAL signal must be supplied
before deassertion of RESET.
At power-up, ensure that the voltage difference between the 3.3 V tolerant pins and the chip V
never exceeds a TBD voltage.
C
V
f
Set the EBD bit when not accessing external memory.
Minimize external memory accesses and use internal memory accesses.
Minimize the number of pins that are switching.
Minimize the capacitive load on the pins.
Connect the unused inputs to pull-up or pull-down resistors.
Disable unused peripherals.
For a Port A address pin loaded with 50 pF capacitance, operating at 3.3 V, and with a 100 MHz clock,
toggling at its maximum possible rate (50 MHz), the current consumption is
CCItyp
Power Consumption Considerations
= node/pin capacitance
= voltage swing
= frequency of node/pin toggle
) value reflects the average switching of the internal buses on typical operating conditions.
I
=
CCI
50 10
max) value reflects the typical possible switching of the internal buses
Example 1. Power Consumption
DSP56367 Technical Data, Rev. 2.1
×
CC
–
12
and GND circuits.
I
×
=
3.3
C V
×
×
50
×
×
f
CCP
10
6
and GND
=
8.25mA
Power Consumption Considerations
P
pins.
CC
5-3