DSPD56367PV150 Freescale Semiconductor, DSPD56367PV150 Datasheet - Page 7

• Manufacturer Part Number: DSPD56367PV150
• Manufacturer: Freescale Semiconductor

Specifications of DSPD56367PV150

• Device Core Size: 24b
• Format: Fixed Point
• Clock Freq (max): 150MHz
• Mips: 150
• Device Input Clock Speed: 150MHz
• Ram Size: 69KB
• Program Memory Size: 120KB
• Operating Supply Voltage (typ): 1.8/3.3V
• Operating Supply Voltage (min): 1.71/3.14V
• Operating Supply Voltage (max): 1.89/3.46V
• Operating Temp Range: -40C to 95C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 144
• Package Type: LQFP
• Lead Free Status / Rohs Status: Not Compliant

2.2
2.3
Freescale Semiconductor
Ground Name
Power Name
V
GND
V
GND
GND
V
V
V
V
CCQH
CCQL
GND
CCA
CCD
CCC
V
CCS
V
CCH
CCP
Q
D
A
(3)
(4)
(2)
(2)
P
(4)
(4)
(4)
(4)
(3)
Power
Ground
PLL Power—V
be provided with an extremely low impedance path to the V
Quiet Core (Low) Power—V
tied externally to all other V
The user must provide adequate external decoupling capacitors. There are four V
Quiet External (High) Power—V
to all other chip power inputs.The user must provide adequate decoupling capacitors. There are three V
inputs.
Address Bus Power—V
be tied externally to all other chip power inputs. The user must provide adequate external decoupling
capacitors. There are three V
Data Bus Power—V
externally to all other chip power inputs. The user must provide adequate external decoupling capacitors.
There are four V
Bus Control Power—V
externally to all other chip power inputs. The user must provide adequate external decoupling capacitors.
There are two V
Host Power—V
other chip power inputs. The user must provide adequate external decoupling capacitors. There is one V
input.
SHI, ESAI, ESAI_1, DAX and Timer Power —V
and Timer. This input must be tied externally to all other chip power inputs. The user must provide adequate
external decoupling capacitors. There are two V
PLL Ground—GND
extremely low-impedance path to ground. V
as close as possible to the chip package. There is one GND
Quiet Ground—GND
externally to all other chip ground connections. The user must provide adequate external decoupling
capacitors. There are four GND
Address Bus Ground—GND
connection must be tied externally to all other chip ground connections. The user must provide adequate
external decoupling capacitors. There are four GND
Data Bus Ground—GND
must be tied externally to all other chip ground connections. The user must provide adequate external
decoupling capacitors. There are four GND
CCP
CCC
CCH
CCD
is V
P
inputs.
is an isolated power for the HDI08 I/O drivers. This input must be tied externally to all
CCD
inputs.
Q
is a ground dedicated for PLL use. The connection should be provided with an
CC
is an isolated ground for the internal processing logic. This connection must be tied
CCC
CCA
is an isolated power for sections of the data bus I/O drivers. This input must be tied
D
dedicated for PLL use. The voltage should be well-regulated and the input should
DSP56367 Technical Data, Rev. 2.1
CCQL
is an isolated ground for sections of the data bus I/O drivers. This connection
is an isolated power for the bus control I/O drivers. This input must be tied
is an isolated power for sections of the address bus I/O drivers. This input must
CCQL
CCA
A
Table 2-2 Power Inputs
Q
is an isolated ground for sections of the address bus I/O drivers. This
power pins and the V
CCQH
connections.
inputs.
Table 2-3 Grounds
is an isolated power for the internal processing logic. This input must be
is a quiet power source for I/O lines. This input must be tied externally
CCP
D
connections.
should be bypassed to GND
Description
Description
CCS
CCS
A
inputs.
is an isolated power for the SHI, ESAI, ESAI_1, DAX
connections.
CCP
power pin only. Do not tie with other power pins.
CC
P
connection.
power rail. There is one V
P
by a 0.47 µF capacitor located
CCQL
inputs.
CCP
input.
CCQH
Power
CCH
2-3