DSPD56367PV150 Freescale Semiconductor, DSPD56367PV150 Datasheet - Page 37

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DSPD56367PV150

Manufacturer Part Number
DSPD56367PV150
Description
Manufacturer
Freescale Semiconductor
Datasheet

Specifications of DSPD56367PV150

Device Core Size
24b
Format
Fixed Point
Clock Freq (max)
150MHz
Mips
150
Device Input Clock Speed
150MHz
Ram Size
69KB
Program Memory Size
120KB
Operating Supply Voltage (typ)
1.8/3.3V
Operating Supply Voltage (min)
1.71/3.14V
Operating Supply Voltage (max)
1.89/3.46V
Operating Temp Range
-40C to 95C
Operating Temperature Classification
Industrial
Mounting
Surface Mount
Pin Count
144
Package Type
LQFP
Lead Free Status / Rohs Status
Not Compliant

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
DSPD56367PV150
Manufacturer:
MOT
Quantity:
60
Part Number:
DSPD56367PV150K41R
Manufacturer:
DSP
Quantity:
59
1
2
3
Freescale Semiconductor
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
No.
WS is the number of wait states specified in the BCR. The value is given for the minimum for a given category. (For example,
for a category of [2 ≤ WS ≤ 7] timing is specified for 2 wait states.) Two wait states is the minimum otherwise.
Timings 100, 107 are guaranteed by design, not tested.
In the case of TA negation: timing 118 is relative to the deassertion edge of RD or WR were TA to remain active.
Address and AA valid to input data valid
RD assertion to input data valid
RD deassertion to data not valid (data hold time)
Address valid to WR deassertion
Data valid to WR deassertion (data setup time)
Data hold time from WR deassertion
WR assertion to data active
WR deassertion to data high impedance
Previous RD deassertion to data active (write)
RD deassertion time
WR deassertion time
Address valid to RD assertion
RD assertion pulse width
RD deassertion to address not valid
TA setup before RD or WR deassertion
TA hold after RD or WR deassertion
Characteristics
Table 3-8 SRAM Read and Write Accesses (continued)
2
DSP56367 Technical Data, Rev. 2.1
3
t
Symbol
DS
t
AA
t
t
t
OHZ
t
OE
AW
DH
, t
(t
DW
AC
) (WS − 0.25) × T
(WS + 0.75) × T
(WS + 0.25) × T
(WS + 0.75) × T
0.25 × T
1.25 × T
0.25 × T
1.25 × T
2.25 × T
1.75 × T
1.25 × T
1.25 × T
2.5 × T
2.0 × T
−0.25 × T
2.25 × T
2.25 × T
3.25 × T
2.75 × T
2.25 × T
3.5 × T
(WS + 0.25) × T
0.25 × T
0.5 × T
Expression
C
C
C
C
C
C
C
C
C
C
− 4.0 [4 ≤ WS ≤ 7]
− 4.0 [2 ≤ WS ≤ 3]
C
+ 0.2 [2 ≤ WS ≤ 3]
+ 0.2 [4 ≤ WS ≤ 7]
C
C
− 3.7 [2 ≤ WS ≤ 3]
− 4.0 [2 ≤ WS ≤ 3]
− 4.0 [4 ≤ WS ≤ 7]
C
− 4.0 [2 ≤ WS ≤ 7]
C
− 2.0 [2 ≤ WS ≤ 7]
C
− 2.0[2 ≤ WS ≤ 7]
C
External Memory Expansion Port (Port A)
− 4.0 [WS ≥ 8]
+ 0.2 [WS ≥ 8]
− 2.0 [WS ≥ 8]
− 4.0 [WS ≥ 8]
− 4.0 [WS ≥ 8]
− 2.0 [WS ≥ 8]
− 3.7 [WS ≥ 4]
C
C
C
C
C
C
− 3.0 [WS ≥ 2]
− 5.0 [WS ≥ 2]
− 5.0 [WS ≥ 2]
− 4.0 [WS ≥ 2]
− 2.0
+ 2.0
C
1
−4.0
14.3
13.0
11.0
17.7
14.3
12.7
19.3
11.0
13.0
Min
-2.0
-5.4
0.0
8.7
6.3
4.3
7.7
9.3
1.3
6.3
3.7
0.0
150 MHz
Max
13.3
10.0
15.2
1.9
8.5
Unit
3-13
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns

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