LPC1857FET256,551 NXP Semiconductors, LPC1857FET256,551 Datasheet - Page 1060

• Manufacturer Part Number: LPC1857FET256,551
• Description: IC MCU 32BIT 1MB FLASH 256LBGA
• Manufacturer: NXP Semiconductors
• Series: LPC18xxr

Specifications of LPC1857FET256,551

• Core Processor: ARM® Cortex-M3™
• Core Size: 32-Bit
• Speed: 150MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, Microwire, SD/MMC, SPI, SSI, SSP, UART/USART, USB OTG
• Peripherals: Brown-out Detect/Reset, DMA, I²S, LCD, Motor Control PWM, POR, PWM, WDT
• Number Of I /o: 80
• Program Memory Size: 1MB (1M x 8)
• Program Memory Type: FLASH
• Eeprom Size: -
• Ram Size: 136K x 8
• Voltage - Supply (vcc/vdd): 2 V ~ 3.6 V
• Data Converters: A/D 16x10b; D/A 1x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 256-LBGA
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

NXP Semiconductors
<Document ID>
User manual
42.8.4.5 GPIO port output clear register (CLR)
Table 987. GPIO port output set register (SET0 to SET4 - addresses 0x400F 0018 to 0x400F
Aside from the 32-bit long and word only accessible FIOSET register, every GPIO port
can also be controlled via two byte and one half-word accessible register listed in
Table
registers allow easier and faster access to the physical port pins.
Table 988. GPIO port output set byte and half-word accessible register description
FIOCLR is used to produce a LOW level output at port pins configured as GPIO in output
mode. Writing 1 produces a LOW level at the corresponding port pin and clears the
corresponding bit in the SET register. Writing 0 has no effect. If any pin is configured as an
input or a secondary function, writing to CLR has no effect.
The CLR is a write-only register.
Access to a port pin via the FIOCLR register is masked by the corresponding bit of the
MASK register (see
Bit
15:0
31:16 -
Generic
register
name
SETn_0
SETn_1
SETn_L
988. Next to providing the same functions as the FIOSET register, these additional
Symbol
SETPIN
0098) bit description
Description
GPIO port x output set register 0.
Bit 0 corresponds to
pinGPIOx_0... bit 7 to pin
GPIOx_7.
GPIO port x output set register 1.
Bit 0 corresponds to pin Px.8... bit
7 to pin Px.15.
GPIO port x output set Lower
half-word register. Bit 0 in
corresponds to pin GPIOx_0... bit
15 to pin GPIOx_15.
All information provided in this document is subject to legal disclaimers.
Description
GPIO output value set bits. Bit 0 controls pin GPIOx_0, bit 15 controls
pin GPIOx_15.
0 =
Controlled pin output is unchanged.
1 = Controlled pin output is set to HIGH.
Reserved.
Section
Rev. 00.13 — 20 July 2011
42.8.4.2).
Register
length in
bits
/access
8 (byte)/
R/W
8 (byte)/
R/W
16
(half-word)/
R/W
Reset
value
0x00
0x00
0x0000 SET0_L - 0x400F 0018
Port x register name -
address
SET0_0 - 0x400F 0018
SET1_0 - 0x400F 0038
SET2_0 - 0x400F 0058
SET3_0 - 0x400F 0078
SET4_0 - 0x400F 0098
SET0_1 - 0x400F 0019
SET1_1 - 0x400F 0039
SET2_1 - 0x400F 0059
SET3_1 - 0x400F 0079
SET4_1 - 0x400F 0099
SET1_L - 0x400F 0038
SET2_L - 0x400F 0058
SET3_L - 0x400F 0078
SET4_L - 0x400F 0098
Chapter 42: Appendix
UM10430
© NXP B.V. 2011. All rights reserved.
1060 of 1164
Reset
value
0x0
-