LPC1857FET256,551 NXP Semiconductors, LPC1857FET256,551 Datasheet - Page 220

• Manufacturer Part Number: LPC1857FET256,551
• Description: IC MCU 32BIT 1MB FLASH 256LBGA
• Manufacturer: NXP Semiconductors
• Series: LPC18xxr

Specifications of LPC1857FET256,551

• Core Processor: ARM® Cortex-M3™
• Core Size: 32-Bit
• Speed: 150MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, Microwire, SD/MMC, SPI, SSI, SSP, UART/USART, USB OTG
• Peripherals: Brown-out Detect/Reset, DMA, I²S, LCD, Motor Control PWM, POR, PWM, WDT
• Number Of I /o: 80
• Program Memory Size: 1MB (1M x 8)
• Program Memory Type: FLASH
• Eeprom Size: -
• Ram Size: 136K x 8
• Voltage - Supply (vcc/vdd): 2 V ~ 3.6 V
• Data Converters: A/D 16x10b; D/A 1x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 256-LBGA
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

14.1 How to read this chapter
14.2 Basic configuration
14.3 General description
<Document ID>
User manual
Remark: This chapter describes parts LPC1850/30/20/10 Rev ‘A’.
Remark: The VADC block is not available on the LPC1850/30/20/10 Rev ‘A’.
The GIMA is configured as follows:
Table 132. GIMA clocking and power control
The Global Input Multiplexer Array (GIMA) provides an internal crosslink multiplexer array
to connect and synchronize inputs from the pads or internal inputs to event driven
peripherals such as the timers, the ADC, or the event router.
The GIMA has 30 outputs, each of which is connected to a peripheral function like a timer
capture input or the ADC conversion start input. One register for each output configures
the input and controls the synchronizer.
Table 133. GIMA inputs
Clock to GIMA register interface
Input
0
1
4:2
5
6
7
8
9
10
11
12
13
•
•
•
UM10430
Chapter 14: LPC18xx Global Input Multiplexer Array (GIMA)
Rev. 00.13 — 20 July 2011
See
The GIMA is reset by the GIMA_RST (reset # <tbd>).
The GIMA outputs are connected to the timer, SCT, ADC, and event router
peripherals (see
Source
GPIO6[28]
GPIO5[3]
reserved
MCOB2
pin CTIN_0
pin CTIN_1
pin CTIN_2
pin CTIN_3
pin CTIN_4
pin CTIN_5
pin CTIN_6
pin CTIN_7
Table 132
All information provided in this document is subject to legal disclaimers.
for clocking and power control.
Figure 24
Rev. 00.13 — 20 July 2011
and
Possible connections to peripheral blocks
VADC
VADC
-
VADC
T0 CAP0
T0 CAP1
T0 CAP2
T1 CAP1
T1 CAP2
T2 CAP2
T3 CAP1
T3 CAP2
Figure
Base clock
BASE_M3_CLK
25).
T1 CAP0
T2 CAP1
SCT CAP2
SCT CAP3
SCT CAP4
SCT CAP5
SCT CAP6
SCT CAP7
Branch clock
CLK_M3_BUS
T3 CAP0
SCT CAP1
© NXP B.V. 2011. All rights reserved.
User manual
SCT CAP0
Maximum
frequency
150 MHz
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