LPC1857FET256,551 NXP Semiconductors, LPC1857FET256,551 Datasheet - Page 842

• Manufacturer Part Number: LPC1857FET256,551
• Description: IC MCU 32BIT 1MB FLASH 256LBGA
• Manufacturer: NXP Semiconductors
• Series: LPC18xxr

Specifications of LPC1857FET256,551

• Core Processor: ARM® Cortex-M3™
• Core Size: 32-Bit
• Speed: 150MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, Microwire, SD/MMC, SPI, SSI, SSP, UART/USART, USB OTG
• Peripherals: Brown-out Detect/Reset, DMA, I²S, LCD, Motor Control PWM, POR, PWM, WDT
• Number Of I /o: 80
• Program Memory Size: 1MB (1M x 8)
• Program Memory Type: FLASH
• Eeprom Size: -
• Ram Size: 136K x 8
• Voltage - Supply (vcc/vdd): 2 V ~ 3.6 V
• Data Converters: A/D 16x10b; D/A 1x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 256-LBGA
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

NXP Semiconductors
<Document ID>
User manual
36.7.3 CAN message handler
The last two functions, combined with the readable CAN receive pin CAN_RXD, can be
used to check the CAN bus’ physical layer.
The output mode of pin CAN_TXD is selected by programming the Test Register bits TX1
and TX0 as described
Remark: The three test functions for pin CAN_TXD interfere with all CAN protocol
functions. The CAN_TXD pin must be left in its default function when CAN message
transfer or any of the test modes Loo-back mode, Silent mode, or Basic mode are
selected.
The Message handler controls the data transfer between the Rx/Tx Shift Register of the
CAN Core, the Message RAM and the IFx Registers, see
The message handler controls the following functions:
2. drives CAN sample point signal to monitor the CAN controller’s timing.
3. drives recessive constant value.
4. drives dominant constant value.
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Data Transfer between IFx Registers and the Message RAM
Data Transfer from Shift Register to the Message RAM
Data Transfer from Message RAM to Shift Register
Data Transfer from Shift Register to the Acceptance Filtering unit
Scanning of Message RAM for a matching Message Object
Handling of TXRQST flags
Handling of interrupts
All information provided in this document is subject to legal disclaimers.
Rev. 00.13 — 20 July 2011
Section
36.6.1.6.
Figure
Chapter 36: LPC18xx C_CAN
124.
UM10430
© NXP B.V. 2011. All rights reserved.
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