LPC1857FET256,551 NXP Semiconductors, LPC1857FET256,551 Datasheet - Page 329
LPC1857FET256,551
Manufacturer Part Number
LPC1857FET256,551
Description
IC MCU 32BIT 1MB FLASH 256LBGA
Manufacturer
NXP Semiconductors
Series
LPC18xxr
Datasheets
1.LPC1830FET256551.pdf
(87 pages)
2.LPC1810FET100551.pdf
(2 pages)
3.LPC1810FET100551.pdf
(1164 pages)
Specifications of LPC1857FET256,551
Core Processor
ARM® Cortex-M3™
Core Size
32-Bit
Speed
150MHz
Connectivity
CAN, EBI/EMI, Ethernet, I²C, Microwire, SD/MMC, SPI, SSI, SSP, UART/USART, USB OTG
Peripherals
Brown-out Detect/Reset, DMA, I²S, LCD, Motor Control PWM, POR, PWM, WDT
Number Of I /o
80
Program Memory Size
1MB (1M x 8)
Program Memory Type
FLASH
Eeprom Size
-
Ram Size
136K x 8
Voltage - Supply (vcc/vdd)
2 V ~ 3.6 V
Data Converters
A/D 16x10b; D/A 1x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
256-LBGA
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Available stocks
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Part Number
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Part Number:
LPC1857FET256,551
Manufacturer:
NXP Semiconductors
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User manual
19.7.3 EMC Configuration register
19.7.4 Dynamic Memory Control register
Table 267. EMC Status register (STATUS - address 0x4000 5008) bit description
The Config register configures the operation of the memory controller. It is recommended
that this register is modified during system initialization, or when there are no current or
outstanding transactions. This can be ensured by waiting until the EMC is idle, and then
entering low-power, or disabled mode. This register is accessed with one wait state.
Table 268. EMC Configuration register (CONFIG - address 0x4000 5008) bit description
The DynamicControl register controls dynamic memory operation. The control bits can be
altered during normal operation.
Table 269. Dynamic Control register (DYNAMICCONTROL - address 0x4000 5020) bit
Bit
2
31:3 -
Bit
0
7:1
8
31:9 -
Bit
0
Symbol
EM
-
Symbol
CR
SA
Symbol
CE
description
All information provided in this document is subject to legal disclaimers.
Value
0
1
-
Value Description
0
1
-
0
1
-
Value Description
0
1
Rev. 00.13 — 20 July 2011
Endian mode.
Little-endian mode (POR reset value).
Big-endian mode.
On power-on reset, the value of the endian bit is 0. All data must
be flushed in the EMC before switching between little-endian and
big-endian modes.
Reserved, user software should not write ones to reserved bits.
The value read from a reserved bit is not defined.
Clock Ratio. CCLK: CLKOUT[1:0] ratio:
1:1 (POR reset value)
1:2
This bit must contain 0 for proper operation of the EMC.
Reserved, user software should not write ones to reserved bits.
The value read from a reserved bit is not defined.
Dynamic memory clock enable.
Clock enable of idle devices are deasserted to save power (POR
reset value).
All clock enables are driven HIGH continuously.
Description
Self-refresh acknowledge. This bit indicates the operating
mode of the EMC:
Normal mode
Self-refresh mode (POR reset value).
Reserved, user software should not write ones to reserved
bits. The value read from a reserved bit is not defined.
Chapter 19: LPC18xx External Memory Controller (EMC)
[1]
UM10430
© NXP B.V. 2011. All rights reserved.
329 of 1164
Reset
value
1
-
Reset
value
0
-
0
-
Reset
value
0
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