LPC1857FET256,551 NXP Semiconductors, LPC1857FET256,551 Datasheet - Page 522
LPC1857FET256,551
Manufacturer Part Number
LPC1857FET256,551
Description
IC MCU 32BIT 1MB FLASH 256LBGA
Manufacturer
NXP Semiconductors
Series
LPC18xxr
Datasheets
1.LPC1830FET256551.pdf
(87 pages)
2.LPC1810FET100551.pdf
(2 pages)
3.LPC1810FET100551.pdf
(1164 pages)
Specifications of LPC1857FET256,551
Core Processor
ARM® Cortex-M3™
Core Size
32-Bit
Speed
150MHz
Connectivity
CAN, EBI/EMI, Ethernet, I²C, Microwire, SD/MMC, SPI, SSI, SSP, UART/USART, USB OTG
Peripherals
Brown-out Detect/Reset, DMA, I²S, LCD, Motor Control PWM, POR, PWM, WDT
Number Of I /o
80
Program Memory Size
1MB (1M x 8)
Program Memory Type
FLASH
Eeprom Size
-
Ram Size
136K x 8
Voltage - Supply (vcc/vdd)
2 V ~ 3.6 V
Data Converters
A/D 16x10b; D/A 1x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
256-LBGA
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
LPC1857FET256,551
Manufacturer:
NXP Semiconductors
Quantity:
10 000
- Current page: 522 of 1164
- Download datasheet (8Mb)
NXP Semiconductors
<Document ID>
User manual
22.8.2.3 Transmit frame processing
22.8.2.4 Transmit polling suspended
The Transmit DMA expects that the data buffers contain complete Ethernet frames,
excluding preamble, pad bytes, and FCS fields. The DA, SA, and Type/Len fields contain
valid data. If the Transmit Descriptor indicates that the MAC core must disable CRC or
PAD insertion, the buffer must have complete Ethernet frames (excluding preamble),
including the CRC bytes.
Frames can be data-chained and can span several buffers. Frames must be delimited by
the First Descriptor (TDES1[29]) and the Last Descriptor (TDES1[30]), respectively.
As transmission starts, the First Descriptor must have (TDES1[29]) set. When this occurs,
frame data transfers from the Host buffer to the MTL Transmit FIFO. Concurrently, if the
current frame has the Last Descriptor (TDES1[30]) clear, the Transmit Process attempts
to acquire the Next Descriptor. The Transmit Process expects this descriptor to have
TDES1[29] clear. If TDES1[30] is clear, it indicates an intermediary buffer. If TDES1[30] is
set, it indicates the last buffer of the frame.
After the last buffer of the frame has been transmitted, the DMA writes back the final
status information to the Transmit Descriptor 0 (TDES0) word of the descriptor that has
the last segment set in Transmit Descriptor 1 (TDES1[30]). At this time, if Interrupt on
Completion (TDES1[31]) was set, Transmit Interrupt (DMA Status register, bit 0) is set, the
Next Descriptor is fetched, and the process repeats.
The actual frame transmission begins after the MTL Transmit FIFO has reached either a
programmable transmit threshold (DMA Operation Mode register, bits [16:14]), or a full
frame is contained in the FIFO. There is also an option for Store and Forward Mode (DMA
Operation Mode register, bit [21]). Descriptors are released (Own bit TDES0[31] clears)
when the DMA finishes transferring the frame.
Remark: To ensure proper transmission of a frame and the next frame, you must specify
a non-zero buffer size for the transmit descriptor that has the Last Descriptor (TDES1[30])
set.
Transmit polling can be suspended by either of the following conditions:
If the second condition occur, both Abnormal Interrupt Summary (DMA Status register
Table
information is written to Transmit Descriptor 0, causing the suspension. If the DMA goes
into SUSPEND state because of the first condition, then both Normal Interrupt Summary
(DMA Status register
Table
In both cases, the position in the Transmit List is retained. The retained position is that of
the descriptor following the Last Descriptor closed by the DMA.
•
•
The DMA detects a descriptor owned by the Host (TDES0[31]=0). To resume, the
driver must give descriptor ownership to the DMA and then issue a Poll Demand
command.
A frame transmission is aborted when a transmit error because of underflow is
detected. The appropriate Transmit Descriptor 0 (TDES0) bit is set.
427) and Transmit Underflow bits (DMA Status register
427) are set.
All information provided in this document is subject to legal disclaimers.
Table
Rev. 00.13 — 20 July 2011
427) and Transmit Buffer Unavailable (DMA Status register
Chapter 22: LPC18xx Ethernet
Table
427) are set, and the
UM10430
© NXP B.V. 2011. All rights reserved.
522 of 1164
Related parts for LPC1857FET256,551
Image
Part Number
Description
Manufacturer
Datasheet
Request
R
Part Number:
Description:
NXP Semiconductors designed the LPC2420/2460 microcontroller around a 16-bit/32-bitARM7TDMI-S CPU core with real-time debug interfaces that include both JTAG andembedded trace
Manufacturer:
NXP Semiconductors
Datasheet:
Part Number:
Description:
NXP Semiconductors designed the LPC2458 microcontroller around a 16-bit/32-bitARM7TDMI-S CPU core with real-time debug interfaces that include both JTAG andembedded trace
Manufacturer:
NXP Semiconductors
Datasheet:
Part Number:
Description:
NXP Semiconductors designed the LPC2468 microcontroller around a 16-bit/32-bitARM7TDMI-S CPU core with real-time debug interfaces that include both JTAG andembedded trace
Manufacturer:
NXP Semiconductors
Datasheet:
Part Number:
Description:
NXP Semiconductors designed the LPC2470 microcontroller, powered by theARM7TDMI-S core, to be a highly integrated microcontroller for a wide range ofapplications that require advanced communications and high quality graphic displays
Manufacturer:
NXP Semiconductors
Datasheet:
Part Number:
Description:
NXP Semiconductors designed the LPC2478 microcontroller, powered by theARM7TDMI-S core, to be a highly integrated microcontroller for a wide range ofapplications that require advanced communications and high quality graphic displays
Manufacturer:
NXP Semiconductors
Datasheet:
Part Number:
Description:
The Philips Semiconductors XA (eXtended Architecture) family of 16-bit single-chip microcontrollers is powerful enough to easily handle the requirements of high performance embedded applications, yet inexpensive enough to compete in the market for hi
Manufacturer:
NXP Semiconductors
Datasheet:
Part Number:
Description:
The Philips Semiconductors XA (eXtended Architecture) family of 16-bit single-chip microcontrollers is powerful enough to easily handle the requirements of high performance embedded applications, yet inexpensive enough to compete in the market for hi
Manufacturer:
NXP Semiconductors
Datasheet:
Part Number:
Description:
The XA-S3 device is a member of Philips Semiconductors? XA(eXtended Architecture) family of high performance 16-bitsingle-chip microcontrollers
Manufacturer:
NXP Semiconductors
Datasheet:
Part Number:
Description:
The NXP BlueStreak LH75401/LH75411 family consists of two low-cost 16/32-bit System-on-Chip (SoC) devices
Manufacturer:
NXP Semiconductors
Datasheet:
Part Number:
Description:
The NXP LPC3130/3131 combine an 180 MHz ARM926EJ-S CPU core, high-speed USB2
Manufacturer:
NXP Semiconductors
Datasheet:
Part Number:
Description:
The NXP LPC3141 combine a 270 MHz ARM926EJ-S CPU core, High-speed USB 2
Manufacturer:
NXP Semiconductors
Part Number:
Description:
The NXP LPC3143 combine a 270 MHz ARM926EJ-S CPU core, High-speed USB 2
Manufacturer:
NXP Semiconductors
Part Number:
Description:
The NXP LPC3152 combines an 180 MHz ARM926EJ-S CPU core, High-speed USB 2
Manufacturer:
NXP Semiconductors
Part Number:
Description:
The NXP LPC3154 combines an 180 MHz ARM926EJ-S CPU core, High-speed USB 2
Manufacturer:
NXP Semiconductors
Part Number:
Description:
Standard level N-channel enhancement mode Field-Effect Transistor (FET) in a plastic package using NXP High-Performance Automotive (HPA) TrenchMOS technology
Manufacturer:
NXP Semiconductors
Datasheet: