LPC1857FET256,551 NXP Semiconductors, LPC1857FET256,551 Datasheet - Page 396
LPC1857FET256,551
Manufacturer Part Number
LPC1857FET256,551
Description
IC MCU 32BIT 1MB FLASH 256LBGA
Manufacturer
NXP Semiconductors
Series
LPC18xxr
Datasheets
1.LPC1830FET256551.pdf
(87 pages)
2.LPC1810FET100551.pdf
(2 pages)
3.LPC1810FET100551.pdf
(1164 pages)
Specifications of LPC1857FET256,551
Core Processor
ARM® Cortex-M3™
Core Size
32-Bit
Speed
150MHz
Connectivity
CAN, EBI/EMI, Ethernet, I²C, Microwire, SD/MMC, SPI, SSI, SSP, UART/USART, USB OTG
Peripherals
Brown-out Detect/Reset, DMA, I²S, LCD, Motor Control PWM, POR, PWM, WDT
Number Of I /o
80
Program Memory Size
1MB (1M x 8)
Program Memory Type
FLASH
Eeprom Size
-
Ram Size
136K x 8
Voltage - Supply (vcc/vdd)
2 V ~ 3.6 V
Data Converters
A/D 16x10b; D/A 1x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
256-LBGA
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
LPC1857FET256,551
Manufacturer:
NXP Semiconductors
Quantity:
10 000
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Table 338. USB Endpoint 1 to 5 control registers (ENDPTCTRL - address 0x4000 61C4 (ENDPTCTRL1) to
<Document ID>
User manual
Bit
1
3:2
4
5
6
7
15:8
16
17
19:18 TXT1_0
20
Symbol
-
RXT
-
RXI
RXR
RXE
-
TXS
-
-
0x4000 61D4 (ENDPTCTRL5)) bit description
Value
0x0
0x1
0x2
0x3
-
0
1
0
1
-
0
1
-
0x0
0x1
0x2
0x3
-
Description
Reserved
Endpoint type
Control
Isochronous
Bulk
Reserved
Reserved
Rx data toggle inhibit
This bit is only used for test and should always be written as zero.
Writing a one to this bit will cause this endpoint to ignore the data
toggle sequence and always accept data packets regardless of their
data PID.
Disabled
Enabled
Rx data toggle reset
Write 1 to reset the PID sequence.
Whenever a configuration event is received for this Endpoint,
software must write a one to this bit in order to synchronize the data
PIDs between the host and device.
Rx endpoint enable
Remark: An endpoint should be enabled only after it has been
configured.
Endpoint disabled.
Endpoint enabled.
reserved
Tx endpoint stall
Endpoint ok.
This bit will be cleared automatically upon receipt of a SETUP
request if this Endpoint is configured as a Control Endpoint, and this
bit will continue to be cleared by hardware until the associated
ENDPTSETUPSTAT bit is cleared.
Endpoint stalled
Software can write a one to this bit to force the endpoint to return a
STALL handshake to the Host. It will continue returning STALL until
the bit is cleared by software, or it will automatically be cleared upon
receipt of a new SETUP request.
Reserved
Tx endpoint type
Control
Isochronous
Bulk
Interrupt
reserved
All information provided in this document is subject to legal disclaimers.
Rev. 00.13 — 20 July 2011
Chapter 20: LPC18xx USB0 Host/Device/OTG controller
…continued
Reset
value
0
00
0
0
0
0
0
00
UM10430
© NXP B.V. 2011. All rights reserved.
R/W
R/W
R/W
R/W
Access
R/W
WS
R/W
-
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