LPC1857FET256,551 NXP Semiconductors, LPC1857FET256,551 Datasheet - Page 642
LPC1857FET256,551
Manufacturer Part Number
LPC1857FET256,551
Description
IC MCU 32BIT 1MB FLASH 256LBGA
Manufacturer
NXP Semiconductors
Series
LPC18xxr
Datasheets
1.LPC1830FET256551.pdf
(87 pages)
2.LPC1810FET100551.pdf
(2 pages)
3.LPC1810FET100551.pdf
(1164 pages)
Specifications of LPC1857FET256,551
Core Processor
ARM® Cortex-M3™
Core Size
32-Bit
Speed
150MHz
Connectivity
CAN, EBI/EMI, Ethernet, I²C, Microwire, SD/MMC, SPI, SSI, SSP, UART/USART, USB OTG
Peripherals
Brown-out Detect/Reset, DMA, I²S, LCD, Motor Control PWM, POR, PWM, WDT
Number Of I /o
80
Program Memory Size
1MB (1M x 8)
Program Memory Type
FLASH
Eeprom Size
-
Ram Size
136K x 8
Voltage - Supply (vcc/vdd)
2 V ~ 3.6 V
Data Converters
A/D 16x10b; D/A 1x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
256-LBGA
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
LPC1857FET256,551
Manufacturer:
NXP Semiconductors
Quantity:
10 000
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Table 552. MCPWM Capture Control read address (CAPCON - 0x400A 000C) bit description
<Document ID>
User manual
Bit
0
1
2
3
4
5
6
7
8
9
10
Symbol
CAP0MCI0_RE
CAP0MCI0_FE
CAP0MCI1_RE
CAP0MCI1_FE
CAP0MCI2_RE
CAP0MCI2_FE
CAP1MCI0_RE
CAP1MCI0_FE
CAP1MCI1_RE
CAP1MCI1_FE
CAP1MCI2_RE
26.7.2.1 MCPWM Capture Control read address
26.7.2 PWM Capture Control register
Table 551. MCPWM Control clear address (CON_CLR - 0x400A 0008) bit description
The MCCAPCON register controls detection of events on the MCI0-2 inputs for all
MCPWM channels. Any of the three MCI inputs can be used to trigger a capture event on
any or all of the three channels. This address is read-only, but the underlying register can
be modified by writing to addresses CAPCON_SET and CAPCON_CLR.
Bit
4
7:5
8
9
10
11
12
15:1
3
16
17
18
19
20
28:2
1
29
30
31
Description
A 1 in this bit enables a channel 0 capture event on a rising edge on MCI0.
A 1 in this bit enables a channel 0 capture event on a falling edge on MCI0.
A 1 in this bit enables a channel 0 capture event on a rising edge on MCI1.
A 1 in this bit enables a channel 0 capture event on a falling edge on MCI1.
A 1 in this bit enables a channel 0 capture event on a rising edge on MCI2.
A 1 in this bit enables a channel 0 capture event on a falling edge on MCI2.
A 1 in this bit enables a channel 1 capture event on a rising edge on MCI0.
A 1 in this bit enables a channel 1 capture event on a falling edge on MCI0.
A 1 in this bit enables a channel 1 capture event on a rising edge on MCI1.
A 1 in this bit enables a channel 1 capture event on a falling edge on MCI1.
A 1 in this bit enables a channel 1 capture event on a rising edge on MCI2.
Symbol
DISUP0_CLR
-
RUN1_CLR
CENTER1_CLR
POLA1_CLR
DTE1_CLR
DISUP1_CLR
-
RUN2_CLR
CENTER2_CLR
POLA2_CLR
DTE2_CLR
DISUP2_CLR
-
INVBDC_CLR
ACMOD_CLR
DCMODE_CLR
All information provided in this document is subject to legal disclaimers.
Rev. 00.13 — 20 July 2011
Description
Writing a one clears the corresponding bit in the CON register. -
Writing a one clears the corresponding bit in the CON register. -
Writing a one clears the corresponding bit in the CON register. -
Writing a one clears the corresponding bit in the CON register. -
Writing a one clears the corresponding bit in the CON register. -
Writing a one clears the corresponding bit in the CON register. -
Writing a one clears the corresponding bit in the CON register. -
Writing a one clears the corresponding bit in the CON register. -
Writing a one clears the corresponding bit in the CON register. -
Writing a one clears the corresponding bit in the CON register. -
Writing a one clears the corresponding bit in the CON register. -
Writing a one clears the corresponding bit in the CON register. -
Writing a one clears the corresponding bit in the CON register. -
Writing a one clears the corresponding bit in the CON register. -
Writing a one clears the corresponding bit in the CON register. -
Writing a one clears the corresponding bit in the CON register. -
Writing a one clears the corresponding bit in the CON register.
Chapter 26: LPC18xx Motor Control PWM (MOTOCONPWM)
UM10430
© NXP B.V. 2011. All rights reserved.
642 of 1164
Reset
value
Reset
value
0
0
0
0
0
0
0
0
0
0
0
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