LPC1857FET256,551 NXP Semiconductors, LPC1857FET256,551 Datasheet - Page 452
LPC1857FET256,551
Manufacturer Part Number
LPC1857FET256,551
Description
IC MCU 32BIT 1MB FLASH 256LBGA
Manufacturer
NXP Semiconductors
Series
LPC18xxr
Datasheets
1.LPC1830FET256551.pdf
(87 pages)
2.LPC1810FET100551.pdf
(2 pages)
3.LPC1810FET100551.pdf
(1164 pages)
Specifications of LPC1857FET256,551
Core Processor
ARM® Cortex-M3™
Core Size
32-Bit
Speed
150MHz
Connectivity
CAN, EBI/EMI, Ethernet, I²C, Microwire, SD/MMC, SPI, SSI, SSP, UART/USART, USB OTG
Peripherals
Brown-out Detect/Reset, DMA, I²S, LCD, Motor Control PWM, POR, PWM, WDT
Number Of I /o
80
Program Memory Size
1MB (1M x 8)
Program Memory Type
FLASH
Eeprom Size
-
Ram Size
136K x 8
Voltage - Supply (vcc/vdd)
2 V ~ 3.6 V
Data Converters
A/D 16x10b; D/A 1x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
256-LBGA
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Available stocks
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Part Number
Manufacturer
Quantity
Price
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Part Number:
LPC1857FET256,551
Manufacturer:
NXP Semiconductors
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10 000
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Table 373. USB Interrupt register in host mode (USBINTR_H - address 0x4000 7148) bit description
<Document ID>
User manual
Bit
0
1
2
3
4
5
6
7
8
15:9
16
17
18
19
31:20 -
Symbol Description
UE
UEE
PCE
FRE
-
AAE
-
SRE
-
-
-
-
UAIE
UPIA
21.6.4.2 Host mode
USB interrupt enable
When this bit is one, and the USBINT bit in the USBSTS register is one, the
host/device controller will issue an interrupt at the next interrupt threshold. The
interrupt is acknowledged by software clearing the USBINT bit in USBSTS.
USB error interrupt enable
When this bit is a one, and the USBERRINT bit in the USBSTS register is a one, the
host/device controller will issue an interrupt at the next interrupt threshold. The
interrupt is acknowledged by software clearing the USBERRINT bit in the USBSTS
register.
Port change detect enable
When this bit is a one, and the Port Change Detect bit in the USBSTS register is a
one, the host/device controller will issue an interrupt. The interrupt is acknowledged
by software clearing the Port Change Detect bit in USBSTS.
Frame list rollover enable
When this bit is a one, and the Frame List Rollover bit in the USBSTS register is a
one, the host controller will issue an interrupt. The interrupt is acknowledged by
software clearing the Frame List Rollover bit.
Reserved
Interrupt on asynchronous advance enable
When this bit is a one, and the Interrupt on Async Advance bit in the USBSTS register
is a one, the host controller will issue an interrupt at the next interrupt threshold. The
interrupt is acknowledged by software clearing the Interrupt on Async Advance bit.
Not used by the Host controller.
If this bit is one and the SRI bit in the USBSTS register is one, the host controller will
issue an interrupt. In host mode, the SRI bit will be set every 125 s and can be used
by the host controller as a time base. The interrupt is acknowledged by software
clearing the SRI bit in the USBSTS register.
Not used by the Host controller.
Reserved
Reserved
USB host asynchronous interrupt enable
When this bit is a one, and the USBHSTASYNCINT bit in the USBSTS register is a
one, the host controller will issue an interrupt at the next interrupt threshold. The
interrupt is acknowledged by software clearing the USBHSTASYNCINT bit.
USB host periodic interrupt enable
When this bit is a one, and the USBHSTPERINT bit in the USBSTS register is a one,
the host controller will issue an interrupt at the next interrupt threshold. The interrupt is
acknowledged by software clearing the USBHSTPERINT bit.
Reserved
Not used by the host controller.
All information provided in this document is subject to legal disclaimers.
Rev. 00.13 — 20 July 2011
Chapter 21: LPC18xx USB1 Host/Device controller
UM10430
© NXP B.V. 2011. All rights reserved.
Access Reset
R/W
R/W
R/W
-
R/W
-
-
-
R/W
R/W
R/W
452 of 1164
value
0
0
0
0
0
0
0
0
0
0
0
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