LPC1857FET256,551 NXP Semiconductors, LPC1857FET256,551 Datasheet - Page 939
LPC1857FET256,551
Manufacturer Part Number
LPC1857FET256,551
Description
IC MCU 32BIT 1MB FLASH 256LBGA
Manufacturer
NXP Semiconductors
Series
LPC18xxr
Datasheets
1.LPC1830FET256551.pdf
(87 pages)
2.LPC1810FET100551.pdf
(2 pages)
3.LPC1810FET100551.pdf
(1164 pages)
Specifications of LPC1857FET256,551
Core Processor
ARM® Cortex-M3™
Core Size
32-Bit
Speed
150MHz
Connectivity
CAN, EBI/EMI, Ethernet, I²C, Microwire, SD/MMC, SPI, SSI, SSP, UART/USART, USB OTG
Peripherals
Brown-out Detect/Reset, DMA, I²S, LCD, Motor Control PWM, POR, PWM, WDT
Number Of I /o
80
Program Memory Size
1MB (1M x 8)
Program Memory Type
FLASH
Eeprom Size
-
Ram Size
136K x 8
Voltage - Supply (vcc/vdd)
2 V ~ 3.6 V
Data Converters
A/D 16x10b; D/A 1x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
256-LBGA
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
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Part Number:
LPC1857FET256,551
Manufacturer:
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User manual
42.1.6 Interrupt sources
Table 885
may have one or more interrupt lines to the Vectored Interrupt Controller. Each line may
represent more than one interrupt source, as noted.
Exception numbers relate to where entries are stored in the exception vector table.
Interrupt numbers are used in some other contexts, such as software interrupts.
In addition, the NVIC handles the Non-Maskable Interrupt (NMI). In order for NMI to
operate from an external signal, the NMI function must be connected to the related device
pin (P4_0 or PE_4). When connected, a logic 1 on the pin will cause the NMI to be
processed. For details, refer to the Cortex-M3 User Guide.
Table 885. Connection of interrupt sources to the NVIC
Interrupt
ID
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
lists the interrupt sources for each peripheral function. Each peripheral device
Exception
Number
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
All information provided in this document is subject to legal disclaimers.
Vector
Offset
0x40
0x44
0x48
0x4C
0x50
0x54
0x58
0x5C
0x60
0x64
0x68
0x6C
0x70
0x74
0x78
0x7C
0x80
0x84
0x88
0x8C
0x90
0x94
0x98
0x9C
0xA0
0xA4
0xA8
0xAC
0xB0
Rev. 00.13 — 20 July 2011
Function
DAC
Event router
DMA
-
-
Ethernet
SDIO
LCD
USB0
USB1
SCT
RI timer
Timer0
Timer1
Timer2
Timer3
Motor control PWM
ADC0
I2C0
I2C1
-
ADC1
SSP0
SSP1
UART0
UART1
UART2
UART3
I2S
Flag(s)
Combined interrupt from the event router
sources
Reserved
Reserved
sbd_intr_o Ethernet interrupt
OTG interrupt
SCT combined interrupt
Reserved.
also modem interrupt
also irda interrupt
Chapter 42: Appendix
UM10430
© NXP B.V. 2011. All rights reserved.
939 of 1164
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