LPC1857FET256,551 NXP Semiconductors, LPC1857FET256,551 Datasheet - Page 42
LPC1857FET256,551
Manufacturer Part Number
LPC1857FET256,551
Description
IC MCU 32BIT 1MB FLASH 256LBGA
Manufacturer
NXP Semiconductors
Series
LPC18xxr
Datasheets
1.LPC1830FET256551.pdf
(87 pages)
2.LPC1810FET100551.pdf
(2 pages)
3.LPC1810FET100551.pdf
(1164 pages)
Specifications of LPC1857FET256,551
Core Processor
ARM® Cortex-M3™
Core Size
32-Bit
Speed
150MHz
Connectivity
CAN, EBI/EMI, Ethernet, I²C, Microwire, SD/MMC, SPI, SSI, SSP, UART/USART, USB OTG
Peripherals
Brown-out Detect/Reset, DMA, I²S, LCD, Motor Control PWM, POR, PWM, WDT
Number Of I /o
80
Program Memory Size
1MB (1M x 8)
Program Memory Type
FLASH
Eeprom Size
-
Ram Size
136K x 8
Voltage - Supply (vcc/vdd)
2 V ~ 3.6 V
Data Converters
A/D 16x10b; D/A 1x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
256-LBGA
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
LPC1857FET256,551
Manufacturer:
NXP Semiconductors
Quantity:
10 000
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6.6 Register description
<Document ID>
User manual
6.6.1 Level configuration register
Table 18.
This register works in combination with the edge configuration register EDGE (see
Table
Table 19.
Name
HILO
EDGE
-
CLR_EN
SET_EN
STATUS
ENABLE
CLR_STAT
SET_STAT
Bit
0
1
2
3
21) to configure the level and edge detection for each input to the event router.
Symbol
WAKEUP0_L
WAKEUP1_L
WAKEUP2_L
WAKEUP3_L
Register overview: Event router (base address 0x4004 4000)
Level configuration register (HILO - address 0x4004 4000) bit description
All information provided in this document is subject to legal disclaimers.
R/W
R/W
W
W
R
W
W
Access
-
R
Value Description
0
1
0
1
0
1
0
1
Rev. 00.13 — 20 July 2011
Level detect mode for WAKEUP0 event.
Detect LOW level if bit 0 in the EDGE register is 0. Detect
falling edge if bit 0 in the EDGE register is 1.
Detect HIGH level if bit 0 in the EDGE register is 0. Detect
rising edge if bit 0 in the EDGE register is 1.
Level detect mode for WAKEUP1 event. The
corresponding bit in the EDGE register must be 0.
Detect LOW level if bit 1 in the EDGE register is 0.
Detect HIGH level if bit 1 in the EDGE register is 0. Detect
rising edge if bit 1 in the EDGE register is 1.
Level detect mode for WAKEUP2 event.
Detect LOW level if bit 2 in the EDGE register is 0. Detect
falling edge if bit 2 in the EDGE register is 1.
Detect HIGH level if bit 2 in the EDGE register is 0. Detect
rising edge if bit 2 in the EDGE register is 1.
Level detect mode for WAKEUP3 event.
Detect LOW level if bit 3 in the EDGE register is 0. Detect
falling edge if bit 3 in the EDGE register is 1.
Detect HIGH level if bit 3 in the EDGE register is 0. Detect
rising edge if bit 3 in the EDGE register is 1.
Address
offset
0x000
0x004
0x008 -
0xFD4
0xFD8
0xFDC
0xFE0
0xFE4
0xFE8
0xFEC
Description
Level configuration register
Edge configuration
Reserved
Event clear enable register
Event set enable register
Status register
Enable register
Clear register
Set register
Chapter 6: LPC18xx Event router
UM10430
© NXP B.V. 2011. All rights reserved.
Reset
Value
0x000
0x000
-
0x0
0x0
0x0
0x0
0x0
0x0
42 of 1164
Reset
value
0
0
0
0
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