LPC1857FET256,551 NXP Semiconductors, LPC1857FET256,551 Datasheet - Page 211

• Manufacturer Part Number: LPC1857FET256,551
• Description: IC MCU 32BIT 1MB FLASH 256LBGA
• Manufacturer: NXP Semiconductors
• Series: LPC18xxr

Specifications of LPC1857FET256,551

• Core Processor: ARM® Cortex-M3™
• Core Size: 32-Bit
• Speed: 150MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, Microwire, SD/MMC, SPI, SSI, SSP, UART/USART, USB OTG
• Peripherals: Brown-out Detect/Reset, DMA, I²S, LCD, Motor Control PWM, POR, PWM, WDT
• Number Of I /o: 80
• Program Memory Size: 1MB (1M x 8)
• Program Memory Type: FLASH
• Eeprom Size: -
• Ram Size: 136K x 8
• Voltage - Supply (vcc/vdd): 2 V ~ 3.6 V
• Data Converters: A/D 16x10b; D/A 1x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 256-LBGA
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

NXP Semiconductors
<Document ID>
User manual
13.4.8 EMC clock delay register
13.4.9 EMC control delay register
Table 120. Pin configuration for open-drain I
This register provides a programmable delay for the EMC clock outputs. The delay for
each clock output is approximately 0.5 ns  CLKn_DELAY or 0.5 ns  CKEn_DELAY.
(CLKn_DELAY/CKEn_DELAY = 0x0: delay  0 ns, 0x1: delay  0.5 ns, ..., 0x7: delay 
3.5 ns.)
Table 121. EMC clock delay register (EMCCLKDELAY, address 0x4008 6D00) bit description
This register provides a programmable delay for the EMC control outputs. The delay for
each control output is approximately 0.5 ns  XXX_DELAY. (XXX_DELAY = 0x0: delay  0
ns, 0x1: delay  0.5 ns, ..., 0x7: delay  3.5 ns.)
Bit
1
2
31:3
Bit
2:0
3
6:4
7
10:8
11
14:12
15
18:16
19
22:20
23
26:24
27
30:28
31
Symbol
SCL_EHS
SCL_ECS
-
Symbol
CLK0_DELAY Delay of the EMC_CLK0 clock output.
-
CLK1_DELAY Delay of the EMC_CLK0 clock output.
-
CLK2_DELAY Delay of the EMC_CLK2 clock output.
-
CLK3_DELAY Delay of the EMC_CLK3 clock output.
-
CKE0_DELAY Delay of the EMC_CKEOUT0 clock enable output.
-
CKE1_DELAY Delay of the EMC_CKEOUT1 clock enable output.
-
CKE2_DELAY Delay of the EMC_CKEOUT2 clock enable output.
-
CKE3_DELAY Delay of the EMC_CKEOUT3 clock enable output.
-
6C84) bit description
All information provided in this document is subject to legal disclaimers.
Rev. 00.13 — 20 July 2011
Value
0
1
0
1
Description
Reserved.
Reserved.
Reserved.
Reserved.
Reserved.
Reserved.
Reserved.
Reserved.
Description
Configures I
Standard/Fast mode (400 kbit/s)
High-speed mode (3.4 Mbit/s)
Direction (only applies if SCL_EHS = 1)
Receive
Transmit
Reserved
…continued
Chapter 13: LPC18xx System Control Unit (SCU)
2
2
C0-bus speed for SCL0 pin
C-bus pins register (SFSI2C0, address 0x4008
UM10430
© NXP B.V. 2011. All rights reserved.
Reset
value
0
0
-
Reset
value
0
-
0
-
0
-
0
-
0
-
0
-
0
-
0
-
211 of 1164
Access
R/W
R/W
-
Access
R/W
-
R/W
-
R/W
-
R/W
-
R/W
-
R/W
-
R/W
-
R/W
-