LPC1857FET256,551 NXP Semiconductors, LPC1857FET256,551 Datasheet - Page 2
LPC1857FET256,551
Manufacturer Part Number
LPC1857FET256,551
Description
IC MCU 32BIT 1MB FLASH 256LBGA
Manufacturer
NXP Semiconductors
Series
LPC18xxr
Datasheets
1.LPC1830FET256551.pdf
(87 pages)
2.LPC1810FET100551.pdf
(2 pages)
3.LPC1810FET100551.pdf
(1164 pages)
Specifications of LPC1857FET256,551
Core Processor
ARM® Cortex-M3™
Core Size
32-Bit
Speed
150MHz
Connectivity
CAN, EBI/EMI, Ethernet, I²C, Microwire, SD/MMC, SPI, SSI, SSP, UART/USART, USB OTG
Peripherals
Brown-out Detect/Reset, DMA, I²S, LCD, Motor Control PWM, POR, PWM, WDT
Number Of I /o
80
Program Memory Size
1MB (1M x 8)
Program Memory Type
FLASH
Eeprom Size
-
Ram Size
136K x 8
Voltage - Supply (vcc/vdd)
2 V ~ 3.6 V
Data Converters
A/D 16x10b; D/A 1x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
256-LBGA
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
LPC1857FET256,551
Manufacturer:
NXP Semiconductors
Quantity:
10 000
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Revision history
<Document ID>
User manual
Rev
0.13
Modifications:
0.12
Modifications:
0.11
Modifications:
0.10
Modifications:
0.09
Modifications:
Date
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Location of C_CAN1 reset updated in the RGU (see
Pin P2_7 replaced by pin P2_9 as boot pin in
Pin P2_7 designated as ISP entry pin in
Boot ROM size increased to 64 kB.
Editorial updates.
ISP commands for flashless parts included in
All content relating to LPC1850/30/20/10 rev ‘-’ moved to
Repeater and plain input mode swapped in SFSP registers (see
Chapter 7
Use of divide-by-two clock for EMC added
Bit description of RIT MASK register updated
Overdrive mode removed in bits 1:0 of the PUMUCON register (see
Chapter
Chapter
Register bit description and functional description removed in
Description of MSGVAL bit updated in
MAC_RWAKE_FRFLT register cannot used with bit-banding. See
Description of RMII and MII pins corrected in
Description of Ethernet function in pins P1_16 and PC_8 updated.
AES description removed
CGU PLL0 output updated in
In
In
In
Polarity of the ENABLE bit updated in
WIC replaced by Event router throughout the manual.
Table
Table
Table
175, Pin PC_0: Change function 0 to n.c. and move ENET_RX_CLK to function 3.
175, remove all SDIO functions.
175, change CAN1_RD, CAN1_TD to CAN_RD, CAN_TD.
5,
14,
added.
Chapter
Chapter
Description
Preliminary LPC18xx User manual.
Preliminary LPC18xx User manual.
Preliminary LPC18xx User manual.
Preliminary LPC18xx User manual.
Preliminary LPC18xx User manual.
All information provided in this document is subject to legal disclaimers.
6,
9,
Chapter
Chapter
Chapter 4 “LPC18xx Security
Rev. 00.13 — 20 July 2011
Table
7,
13,
Chapter
107.
Chapter 15
Table 112
Table
Table
14,
(Section
757.
Table
Table 107
Chapter
(Table
Chapter 35
107.
added.
(1= power-down).
401.
19.1).
Table
608).
40.
features”.
and
Chapter
added.
91,
Table
Chapter
Table
Section
42.
Table
8.
Table 32
93,
17. API calls to be added.
Table
413.
42.7.4.1).
LPC18xx user manual
and
97).
UM10430
© NXP B.V. 2011. All rights reserved.
Table
918).
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