LPC1857FET256,551 NXP Semiconductors, LPC1857FET256,551 Datasheet - Page 713
LPC1857FET256,551
Manufacturer Part Number
LPC1857FET256,551
Description
IC MCU 32BIT 1MB FLASH 256LBGA
Manufacturer
NXP Semiconductors
Series
LPC18xxr
Datasheets
1.LPC1830FET256551.pdf
(87 pages)
2.LPC1810FET100551.pdf
(2 pages)
3.LPC1810FET100551.pdf
(1164 pages)
Specifications of LPC1857FET256,551
Core Processor
ARM® Cortex-M3™
Core Size
32-Bit
Speed
150MHz
Connectivity
CAN, EBI/EMI, Ethernet, I²C, Microwire, SD/MMC, SPI, SSI, SSP, UART/USART, USB OTG
Peripherals
Brown-out Detect/Reset, DMA, I²S, LCD, Motor Control PWM, POR, PWM, WDT
Number Of I /o
80
Program Memory Size
1MB (1M x 8)
Program Memory Type
FLASH
Eeprom Size
-
Ram Size
136K x 8
Voltage - Supply (vcc/vdd)
2 V ~ 3.6 V
Data Converters
A/D 16x10b; D/A 1x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
256-LBGA
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Available stocks
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Part Number
Manufacturer
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Price
Company:
Part Number:
LPC1857FET256,551
Manufacturer:
NXP Semiconductors
Quantity:
10 000
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32.4 Pin description
32.5 Register description
<Document ID>
User manual
Table 662. USART0/2/3 pin description
The UART contains registers organized as shown in
Bit (DLAB) is contained in LCR[7] and enables access to the Divisor Latches.
Reset value reflects the data stored in used bits only. It does not include the content of
reserved bits.
Table 663. Register overview: UART0/2/3 (base address: 0x4008 1000, 0x400C 1000, 0x400C
Function name
USART0
U0_RXD
U0_TXD
U0_DIR
U0_UCLK
USART2
U2_RXD
U2_TXD
U2_DIR
U2_UCLK
USART3
U3_RXD
U3_TXD
U3_DIR
U3_UCLK
U3_BAUD
Name
RBR
THR
DLL
DLM
IER
2000)
All information provided in this document is subject to legal disclaimers.
Access Address
RO
WO
R/W
R/W
R/W
Direction
I
O
I/O
I/O
I
O
I/O
I/O
I
O
I/O
I/O
Rev. 00.13 — 20 July 2011
offset
0x000
0x000
0x000
0x004
0x004
Description
Serial Input. Serial receive data.
Serial Output. Serial transmit data.
RS-485/EIA-485 output enable/direction control.
Serial clock input/output for USART0 in synchronous mode.
Serial Input. Serial receive data.
Serial Output. Serial transmit data.
RS-485/EIA-485 output enable/direction control.
Serial clock input/output for USART2 in synchronous mode.
Serial Input. Serial receive data.
Serial Output. Serial transmit data.
RS-485/EIA-485 output enable/direction control.
Serial clock input/output for USART3 in synchronous mode.
<tbd>
Description
Receiver Buffer Register. Contains the next
received character to be read (DLAB = 0).
Transmit Holding Register. The next character to be
transmitted is written here (DLAB = 0).
Divisor Latch LSB. Least significant byte of the baud
rate divisor value. The full divisor is used to
generate a baud rate from the fractional rate divider
(DLAB = 1).
Divisor Latch MSB. Most significant byte of the baud
rate divisor value. The full divisor is used to
generate a baud rate from the fractional rate divider
(DLAB = 1).
Interrupt Enable Register. Contains individual
interrupt enable bits for the 7 potential UART
interrupts (DLAB = 0).
Chapter 32: LPC18xx USART0_2_3
Table
663. The Divisor Latch Access
UM10430
© NXP B.V. 2011. All rights reserved.
713 of 1164
Reset
value
NA
NA
0x01
0x00
0x00
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