LPC1857FET256,551 NXP Semiconductors, LPC1857FET256,551 Datasheet - Page 886
LPC1857FET256,551
Manufacturer Part Number
LPC1857FET256,551
Description
IC MCU 32BIT 1MB FLASH 256LBGA
Manufacturer
NXP Semiconductors
Series
LPC18xxr
Datasheets
1.LPC1830FET256551.pdf
(87 pages)
2.LPC1810FET100551.pdf
(2 pages)
3.LPC1810FET100551.pdf
(1164 pages)
Specifications of LPC1857FET256,551
Core Processor
ARM® Cortex-M3™
Core Size
32-Bit
Speed
150MHz
Connectivity
CAN, EBI/EMI, Ethernet, I²C, Microwire, SD/MMC, SPI, SSI, SSP, UART/USART, USB OTG
Peripherals
Brown-out Detect/Reset, DMA, I²S, LCD, Motor Control PWM, POR, PWM, WDT
Number Of I /o
80
Program Memory Size
1MB (1M x 8)
Program Memory Type
FLASH
Eeprom Size
-
Ram Size
136K x 8
Voltage - Supply (vcc/vdd)
2 V ~ 3.6 V
Data Converters
A/D 16x10b; D/A 1x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
256-LBGA
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
LPC1857FET256,551
Manufacturer:
NXP Semiconductors
Quantity:
10 000
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User manual
Fig 143. Format and states in the Slave Transmitter mode
37.10.5.1 STAT = 0xF8
37.10.5.2 STAT = 0x00
37.10.5 Miscellaneous states
reception of the own
Slave address and
one or more Data
bytes all are
acknowledged
last data byte
transmitted. Switched
to Not Addressed
Slave (AA bit in
I2CON = “0”)
arbitration lost as
Master and
addressed as Slave
DATA
n
There are two STAT codes that do not correspond to a defined I
Table
This status code indicates that no relevant information is available because the serial
interrupt flag, SI, is not yet set. This occurs between other states and when the I
is not involved in a serial transfer.
This status code indicates that a bus error has occurred during an I
bus error is caused when a START or STOP condition occurs at an illegal position in the
format frame. Examples of such illegal positions are during the serial transfer of an
address byte, a data byte, or an acknowledge bit. A bus error may also be caused when
external interference disturbs the internal I
set. To recover from a bus error, the STO flag must be set and SI must be cleared. This
A
824). These are discussed below.
S
from Master to Slave
from Slave to Master
any number of data bytes and their associated
Acknowledge bits
this number (contained in I2STA) corresponds to a defined state of
the I
2
C bus
SLA
All information provided in this document is subject to legal disclaimers.
Rev. 00.13 — 20 July 2011
R
A8H
B0H
A
A
DATA
B8H
2
A
C block signals. When a bus error occurs, SI is
DATA
Chapter 37: LPC18xx I2C-bus interface
C8H
C0H
A
A
P OR S
ALL ONES
2
C hardware state (see
2
C serial transfer. A
UM10430
P OR S
© NXP B.V. 2011. All rights reserved.
886 of 1164
2
C block
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