ST7232AK2-Auto STMicroelectronics, ST7232AK2-Auto Datasheet - Page 102

• Manufacturer Part Number: ST7232AK2-Auto
• Description: 8-bit MCU for automotive, 16 Kbyte Flash, 10-bit ADC, 4 timers, SPI, SCI
• Manufacturer: STMicroelectronics

Specifications of ST7232AK2-Auto

• Hdflash Endurance: 100 cycles, data retention
• Clock Sources: crystal/ceramic resonator oscillators and bypass for external clock
• Four Power Saving Modes: halt, active halt, wait and slow
• Main Clock Controller With: real time base, beep and clock-out capabilities
• Two 16-bit Timers With: 2 input captures, 2 output compares, PWM and pulse generator modes

On-chip peripherals
102/201
Input capture 2 low register (IC2LR)
This is an 8-bit read only register that contains the low part of the counter value (transferred
by the input capture 2 event).
16-bit timer register map and reset values
Table 38.
IC2LR
Timer A: 32
Timer B: 42
Timer A: 31
Timer B: 41
Timer A: 33
Timer B: 43
Timer A: 34
Timer B: 44
Timer A: 35
Timer B: 45
Timer A: 36
Timer B: 46
Timer A: 37
Timer B: 47
Timer A: 3E
Timer B: 4E
Timer A: 3F
Timer B: 4F
Timer A: 38
Timer B: 48
Timer A: 39
Timer B: 49
Timer A: 3A
Timer B: 4A
Timer A: 3B
Timer B: 4B
Timer A: 3C
Timer B: 4C
Timer A: 3D
Timer B: 4D
Address (Hex.) Register label
MSB
R
7
16-bit timer register map and reset values
R
CR1
Reset value
CR2
Reset value
CSR
Reset value
IC1HR
Reset value
IC1LR
Reset value
OC1HR
Reset value
OC1LR
Reset value
OC2HR
Reset value
OC2LR
Reset value
CHR
Reset value
CLR
Reset value
ACHR
Reset value
ACLR
Reset value
IC2HR
Reset value
IC2LR
Reset value
6
R
5
OC1E
ICF1
MSB
MSB
MSB
MSB
MSB
MSB
MSB
MSB
MSB
MSB
MSB
MSB
ICIE
7
0
0
x
x
x
1
0
1
0
1
1
1
1
x
x
OC2E
OCF1
OCIE
R
4
6
0
0
x
x
x
0
0
0
0
1
1
1
1
x
x
TOIE
OPM
TOF
5
0
0
x
x
x
0
0
0
0
1
1
1
1
x
x
R
3
FOLV2
PWM
ICF2
4
0
0
x
x
x
0
0
0
0
1
1
1
1
x
x
FOLV1
OCF2
CC1
R
2
3
0
0
0
0
0
0
1
1
1
1
x
x
x
x
x
OLVL2
TIMD
CC0
Reset value: undefined
2
0
0
0
x
x
0
0
0
0
1
1
1
1
x
x
ST7232Axx-Auto
R
1
IEDG1
IEDG2
1
0
0
0
0
0
0
1
0
1
0
x
x
x
x
x
-
EXEDG
LSB
OLVL1
R
LSB
LSB
LSB
LSB
LSB
LSB
LSB
LSB
LSB
LSB
LSB
LSB
0
0
0
0
x
x
x
0
0
0
0
1
0
1
0
x
x
-