ST7232AK2-Auto STMicroelectronics, ST7232AK2-Auto Datasheet - Page 45

• Manufacturer Part Number: ST7232AK2-Auto
• Description: 8-bit MCU for automotive, 16 Kbyte Flash, 10-bit ADC, 4 timers, SPI, SCI
• Manufacturer: STMicroelectronics

Specifications of ST7232AK2-Auto

• Hdflash Endurance: 100 cycles, data retention
• Clock Sources: crystal/ceramic resonator oscillators and bypass for external clock
• Four Power Saving Modes: halt, active halt, wait and slow
• Main Clock Controller With: real time base, beep and clock-out capabilities
• Two 16-bit Timers With: 2 input captures, 2 output compares, PWM and pulse generator modes

ST7232Axx-Auto
7.2.3
7.2.4
Note:
Non-maskable sources
These sources are processed regardless of the state of the I1 and I0 bits of the CC register
(see
corresponding vector is loaded in the PC register and the I1 and I0 bits of the CC are set to
disable interrupts (level 3). These sources allow the processor to exit halt mode.
●
This software interrupt is serviced when the TRAP instruction is executed. It is serviced
according to the flowchart in
●
The reset source has the highest priority in the ST7. This means that the first current routine
has the highest software priority (level 3) and the highest hardware priority. See
Reset sequence manager
Maskable sources
Maskable interrupt vector sources can be serviced if the corresponding interrupt is enabled
and if its own interrupt software priority (in ISPRx registers) is higher than the one currently
being serviced (I1 and I0 in CC register). If any of these two conditions is false, the interrupt
is latched and thus remains pending.
●
●
The general sequence for clearing an interrupt is based on an access to the status register
followed by a read or write to an associated register.
The clearing sequence resets the internal latch. A pending interrupt (i.e. waiting to be
serviced) is therefore lost if the clear sequence is executed.
TRAP (non maskable software interrupt)
Reset
External interrupts
External interrupts allow the processor to exit from halt low power mode. External
interrupt sensitivity is software selectable through the external interrupt control register
(EICR).
External interrupt triggered on edge is latched and the interrupt request automatically
cleared upon entering the interrupt service routine.
If several input pins of a group connected to the same interrupt line are selected
simultaneously, these are logically ORed.
Peripheral interrupts
Usually the peripheral interrupts cause the MCU to exit from halt mode except those
mentioned in
specific flag is set in the peripheral status registers and if the corresponding enable bit
is set in the peripheral control register.
Figure
14). After stacking the PC, X, A and CC registers (except for reset), the
Table 15: Interrupt mapping
(RSM).
Figure
14.
. A peripheral interrupt occurs when a
Section 6.5:
Interrupts
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