ST7232AK2-Auto STMicroelectronics, ST7232AK2-Auto Datasheet - Page 113

• Manufacturer Part Number: ST7232AK2-Auto
• Description: 8-bit MCU for automotive, 16 Kbyte Flash, 10-bit ADC, 4 timers, SPI, SCI
• Manufacturer: STMicroelectronics

Specifications of ST7232AK2-Auto

• Hdflash Endurance: 100 cycles, data retention
• Clock Sources: crystal/ceramic resonator oscillators and bypass for external clock
• Four Power Saving Modes: halt, active halt, wait and slow
• Main Clock Controller With: real time base, beep and clock-out capabilities
• Two 16-bit Timers With: 2 input captures, 2 output compares, PWM and pulse generator modes

ST7232Axx-Auto
10.4.7
10.4.8
Interrupts
Table 40.
1. The SPI interrupt events are connected to the same interrupt vector (see
SPI registers
Control register (SPICR)
Table 41.
SPI end of transfer event
Master mode fault event
Overrun error
SPICR
generate an interrupt if the corresponding enable control bit is set and the interrupt mask in the CC register
is reset (RIM instruction).
SPIE
R/W
Bit
7
Interrupt event
7
6
5
SPI interrupt control/wake-up capability
SPICR register description
SPE
R/W
Bit name
6
SPR2
SPIE
SPE
SPR2
Event flag
R/W
Serial peripheral interrupt enable
Serial peripheral output enable
Divider enable
5
MODF
SPIF
This bit is set and cleared by software.
0: Interrupt is inhibited
1: An SPI interrupt is generated whenever SPIF = 1, MODF = 1 or
OVR = 1 in the SPICSR register
This bit is set and cleared by software. It is also cleared by hardware
when, in master mode, SS = 0 (see
page
not initially connected to the external pins.
0: I/O pins free for general purpose I/O
1: SPI I/O pin alternate functions enabled
This bit is set and cleared by software and is cleared by reset. It is
used with the SPR[1:0] bits to set the baud rate (see bits [1:0]
below).
0: Divider by 2 enabled
1: Divider by 2 disabled
Note: The SPR2 bit has no effect in slave mode
OVR
110). The SPE bit is cleared by reset, so the SPI peripheral is
MSTR
R/W
4
Enable control bit
SPIE
CPOL
R/W
3
Function
(1)
Exit from wait
CPHA
R/W
Master mode fault (MODF) on
Section 7:
2
Reset value: 0000 xxxx (0xh)
Yes
On-chip peripherals
Interrupts). They
1
SPR[1:0]
Exit from halt
R/W
Yes
No
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