ST7232AK2-Auto STMicroelectronics, ST7232AK2-Auto Datasheet - Page 107

• Manufacturer Part Number: ST7232AK2-Auto
• Description: 8-bit MCU for automotive, 16 Kbyte Flash, 10-bit ADC, 4 timers, SPI, SCI
• Manufacturer: STMicroelectronics

Specifications of ST7232AK2-Auto

• Hdflash Endurance: 100 cycles, data retention
• Clock Sources: crystal/ceramic resonator oscillators and bypass for external clock
• Four Power Saving Modes: halt, active halt, wait and slow
• Main Clock Controller With: real time base, beep and clock-out capabilities
• Two 16-bit Timers With: 2 input captures, 2 output compares, PWM and pulse generator modes

ST7232Axx-Auto
Note:
Note:
Master mode transmit sequence
When software writes to the SPIDR register, the data byte is loaded into the 8-bit shift
register and then shifted out serially to the most significant bit of the MOSI pin first.
When data transfer is complete:
●
●
Clearing the SPIF bit is performed by the following software sequence:
1.
2.
While the SPIF bit is set, all writes to the SPIDR register are inhibited until the SPICSR
register is read.
Slave mode operation
In slave mode, the serial clock is received on the SCK pin from the master device.
To operate the SPI in slave mode:
1.
2.
Slave mode transmit sequence
When software writes to the SPIDR register, the data byte is loaded into the 8-bit shift
register and then shifted out serially to the most significant bit of the MISO pin first.
The transmit sequence begins when the slave device receives the clock signal and the most
significant bit of the data on its MOSI pin.
When data transfer is complete:
●
●
Clearing the SPIF bit is performed by the following software sequence:
1.
2.
While the SPIF bit is set, all writes to the SPIDR register are inhibited until the SPICSR
register is read.
The SPIF bit is set by hardware
An interrupt request is generated if the SPIE bit is set and the interrupt mask in the
CCR register is cleared.
An access to the SPICSR register while the SPIF bit is set
A read to the SPIDR register
Write to the SPICSR register to perform the following actions:
–
–
Write to the SPICR register to clear the MSTR bit and set the SPE bit to enable the SPI
I/O functions.
The SPIF bit is set by hardware
An interrupt request is generated if SPIE bit is set and interrupt mask in the CCR
register is cleared.
An access to the SPICSR register while the SPIF bit is set
A write or a read to the SPIDR register
Select the clock polarity and clock phase by configuring the CPOL and CPHA bits
(see
Note: The slave must have the same CPOL and CPHA settings as the master.
Manage the SS pin as described in
Figure
held low during byte transmission and pulled up between each byte to let the slave
write in the shift register.
Figure
48. If CPHA = 1 SS must be held low continuously. If CPHA = 0 SS must be
50)
Slave select management on page 105
On-chip peripherals
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