ST7232AK2-Auto STMicroelectronics, ST7232AK2-Auto Datasheet - Page 129

• Manufacturer Part Number: ST7232AK2-Auto
• Description: 8-bit MCU for automotive, 16 Kbyte Flash, 10-bit ADC, 4 timers, SPI, SCI
• Manufacturer: STMicroelectronics

Specifications of ST7232AK2-Auto

• Hdflash Endurance: 100 cycles, data retention
• Clock Sources: crystal/ceramic resonator oscillators and bypass for external clock
• Four Power Saving Modes: halt, active halt, wait and slow
• Main Clock Controller With: real time base, beep and clock-out capabilities
• Two 16-bit Timers With: 2 input captures, 2 output compares, PWM and pulse generator modes

ST7232Axx-Auto
Note:
The internal sampling clock of the microcontroller samples the pin value on every falling
edge. Therefore, the internal sampling clock and the time the application expects the
sampling to take place may be out of sync. For example: If the baud rate is 15.625 kbaud (bit
length is 64µs), then the 8th, 9th and 10th samples are at 28µs, 32µs and 36µs respectively
(the first sample starting ideally at 0µs). But if the falling edge of the internal clock occurs
just before the pin value changes, the samples would then be out of sync by ~4µs. This
means the entire bit length must be at least 40µs (36µs for the 10th sample + 4µs for
synchronization with the internal sampling clock).
Clock deviation causes
The causes which contribute to the total deviation are:
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All the deviations of the system should be added and compared to the SCI clock tolerance:
D
Noise error causes
See also description of noise error in
Start bit
The noise flag (NF) is set during start bit reception if one of the following conditions occurs:
1.
2.
Therefore, a valid start bit must satisfy both the above conditions to prevent the noise flag
getting set.
Data bits
The noise flag (NF) is set during normal data bit reception if the following condition occurs:
During the sampling of 16 samples, if all three samples numbered 8, 9 and10 are not the
same. The majority of the 8th, 9th and 10th samples is considered as the bit value.
Therefore, a valid data bit must have samples 8, 9 and 10 at the same value to prevent the
noise flag being set.
TRA
D
transmitter is transmitting at a different baud rate).
D
D
the reception of one complete SCI message assuming that the deviation has been
compensated at the beginning of the message.
D
A valid falling edge is not detected. A falling edge is considered to be valid if the 3
consecutive samples before the falling edge occurs are detected as '1' and, after the
falling edge occurs, during the sampling of the 16 samples, if one of the samples
numbered 3, 5 or 7 is detected as a ‘1’.
During sampling of the 16 samples, if one of the samples numbered 8, 9 or 10 is
detected as a ‘1’.
+ D
TRA
QUANT
REC
TCL
QUANT
: Deviation due to the transmission line (generally due to the transceivers)
: Deviation due to transmitter error (local oscillator error of the transmitter or the
: Deviation of the local oscillator of the receiver. This deviation can occur during
: Error due to the baud rate quantisation of the receiver
+ D
REC
+ D
TCL
< 3.75%
Receiver on page
123.
On-chip peripherals
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