ST7232AK2-Auto STMicroelectronics, ST7232AK2-Auto Datasheet - Page 126

• Manufacturer Part Number: ST7232AK2-Auto
• Description: 8-bit MCU for automotive, 16 Kbyte Flash, 10-bit ADC, 4 timers, SPI, SCI
• Manufacturer: STMicroelectronics

Specifications of ST7232AK2-Auto

• Hdflash Endurance: 100 cycles, data retention
• Clock Sources: crystal/ceramic resonator oscillators and bypass for external clock
• Four Power Saving Modes: halt, active halt, wait and slow
• Main Clock Controller With: real time base, beep and clock-out capabilities
• Two 16-bit Timers With: 2 input captures, 2 output compares, PWM and pulse generator modes

On-chip peripherals
Note:
Note:
126/201
Framing error
A framing error is detected when:
●
●
When the framing error is detected:
●
●
●
The FE bit is reset by a SCISR register read operation followed by a SCIDR register read
operation.
Conventional baud rate generation
The baud rate for the receiver and transmitter (Rx and Tx) are set independently and
calculated as follows:
where:
PR = 1, 3, 4 or 13 (see SCP[1:0] bits)
TR = 1, 2, 4, 8, 16, 32, 64,128 (see SCT[2:0] bits)
RR = 1, 2, 4, 8, 16, 32, 64,128 (see SCR[2:0] bits).
All these bits are in the SCIBRR register (see
Example: If f
receive baud rates are 38400 baud.
The baud rate registers MUST NOT be changed while the transmitter or the receiver is
enabled.
Extended baud rate generation
The extended prescaler option gives a very fine tuning on the baud rate, using a 255 value
prescaler, whereas the conventional baud rate generator retains industry standard software
compatibility.
The extended baud rate generator block diagram is described in
The output clock rate sent to the transmitter or to the receiver is the output from the 16
divider divided by a factor ranging from 1 to 255 set in the SCIERPR or the SCIETPR
register.
The extended prescaler is activated by setting the SCIETPR or SCIERPR register to a value
other than zero.
The stop bit is not recognized on reception at the expected time, following either a de-
synchronization or excessive noise.
A break is received
the FE bit is set by hardware
Data is transferred from the Shift register to the SCIDR register
No interrupt is generated. However this bit rises at the same time as the RDRF bit
which itself generates an interrupt.
CPU
is 8 MHz (normal mode) and if PR = 13 and TR = RR = 1, the transmit and
Tx =
(16
f
CPU
*
PR)
*
TR
Baud rate register (SCIBRR) on page
Rx =
(16
f
CPU
*
PR)
*
RR
Figure
55.
ST7232Axx-Auto
136).